- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365359 > PI6C2509-133 (Pericom Semiconductor Corp.) Low-Noise Phase-Locked Loop Clock Driver with 9 Clock Outputs PDF資料下載
參數(shù)資料
| 型號(hào)： | PI6C2509-133 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Low-Noise Phase-Locked Loop Clock Driver with 9 Clock Outputs |
| 中文描述： | 低噪聲鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器，帶有9時(shí)鐘輸出 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | PI6C2509-133 |
1
PSXXXX 06/01/99
CLK_IN
AV
CC
V
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V
CC
2G
FB_IN
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
1G
FB_OUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Product Pin Configuration
Logic Block Diagram
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C2509-133
Clock Driver with 9 Clock Outputs
Product Description
The PI6C2509-133 is a quiet, low-skew, low-jitter, phase-locked
loop (PLL) clock driver, distributing low-noise clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing 5 clocks for the first bank, and an additional
4 clocks for the second bank.
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AV
CC
to ground.
Product Features
Operating Frequency up to 150 MHz
Low-Noise Phase-Locked Loop Clock Distribution to meet
133 MHz Registered DIMM Synchronous DRAM module
specifications for server/workstation/PC applications
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
Zero Input-to-output delay: Distribute One Clock Input to
one bank of five and one bank of four outputs, with
separate output enables
Low jitter: Cycle-to-Cycle jitter ±75ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V V
CC
Package: Plastic 24-pin TSSOP (L)
24-Pin
L
1G
5
2G
CLK_IN
FB_IN
PLL
AV
CC
FB_OUT
2Y[0:3]
1Y[0:4]
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C2509-133L | Low-Noise Phase-Locked Loop Clock Driver with 9 Clock Outputs |
| PI6C2952FBE | Low Voltage PLL Clock Driver |
| PI6C3991-IJ | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991-5IJ | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991-5J | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2509-133L | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 25MHz to 150MHz 24-Pin TSSOP 制造商:Pericom Semiconductor Corporation 功能描述:6C SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| PI6C2509-133LE | 功能描述:鎖相環(huán) - PLL Zero Delay Clck Drvr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2509-133LEX | 功能描述:鎖相環(huán) - PLL Zero Delay Clck Drvr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2509133LX | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI6C2509-133LX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 25MHz to 150MHz 24-Pin TSSOP T/R |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。