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參數(shù)資料
| 型號(hào)： | PI6C2504AQE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER 4OUT 16-QSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2010 |
| 標(biāo)準(zhǔn)包裝： | 97 |
| 類型： | PLL 時(shí)鐘驅(qū)動(dòng)器 |
| PLL： | 帶旁路 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 134MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 管件 |
BelaSigna 300
http://onsemi.com
3
Figures and Data
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
Voltage at any input pin
0.3
2.0
V
Operating supply voltage (Note 1)
0.9
2.0
V
Operating temperature range (Note 2)
40
85
°C
Storage temperature range (Note 3)
55
85
°C
Caution: Class 2 ESD Sensitivity, JESD22A114B (2000 V)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Functional operation only guaranteed below 0°C for digital core (VDDC) and system voltages above 1.0 V.
2. Parameters may exceed listed tolerances when out of the temperature range 0 to 50°C.
3. Extended range 55 to 125°C for storage temperature is under qualification.
Electrical Performance Specifications
The tests were performed at 20
°C with a clean 1.8 V supply voltage. BelaSigna 300 was running in low voltage mode (VDDC = 1.2 V).
The system clock (SYS_CLK) was set to 5.12 MHz and the sampling frequency is 16 kHz unless otherwise noted.
Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part.
Table 2. ELECTRICAL SPECIFICATIONS
Description
Symbol
Conditions
Min
Typ
Max
Units
Screened
OVERALL
Supply voltage
VBAT
The WLCSP package option
will not operate properly below
1.8 V if it relies on an external
EEPROM powered by VBAT.
0.9
1.8
2.0
V
√
Current consumption
IBAT
Filterbank, 100% CFX usage,
5.12 MHz, 16 kHz
Ambient room temperature
750
mA
√
WDRC, VBAT = 1.8 V
Excludes output drive current
Ambient room temperature
600
mA
√
AEC, VBAT = 1.8 V
Excludes output drive current
Ambient room temperature
2.1
mA
√
Theoretical maximum
Excludes output drive current
Ambient room temperature
10
mA
Deep Sleep current
Ambient room temperature,
VBAT = 1.25 V
26
40
mA
Deep Sleep current
Ambient room temperature,
VBAT = 1.8 V
62
160
mA
√
VREG (1 mF External Capacitor)
Regulated voltage output
VREG
0.95
1.00
1.05
V
√
Regulator PSRR
VREG_PSRR
1 kHz
50
55
dB
Load current
ILOAD
2
mA
Load regulation
LOADREG
6.1
6.5
mV/mA
√
Line regulation
LINEREG
2
5
mV/V
VDBL (1 mF External Capacitor)
Regulated doubled voltage
output
VDBL
1.9
2.0
2.1
V
√
4. DFN Package option can have higher inputreferred noise up to 2 mV worse than the WLCSP. WLCSP specifications listed.
5. CDM only applies to the DFN package.
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