參數(shù)資料
型號(hào): PI6C2402WE
廠商: Pericom
文件頁(yè)數(shù): 2/4頁(yè)
文件大?。?/td> 0K
描述: IC PLL CLOCK DRIVER 8-SOIC
產(chǎn)品培訓(xùn)模塊: Total Timing Technology
標(biāo)準(zhǔn)包裝: 97
類型: PLL 時(shí)鐘驅(qū)動(dòng)器
PLL: 帶旁路
輸入: TTL
輸出: TTL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 134MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
PI6C2402
Phase-Locked Loop Clock Driver
2
PS8418I
11/13/08
Recommended Operating Conditions
Symbol
Test Conditions
Temperature
Min.
Max.
Units
VCC
Supply Voltage
Commercial
3.0
3.6
V
Industrial
3.135
3.465
VIH
High Level input voltage
2.0
VIL
Low Level input voltage
0.8
VI
Input voltage
0
VCC
TA
Operating free-air temperature
Commercial
0
70
C
Industrial
-40
85
Absolute Maximum Ratings(1) (Over operating free-air temperature range)
Symbol
Test Conditions
Min.
Max.
Units
VI
Input voltage range
-0.5
VCC + 0.5
V
VO
Output voltage range
-0.5
VCC + 0.5
VI_DC
DC input voltage
-0.5
5.0
IO_DC
DC output current
100
mA
Power
Maximum power dissipation at TA = 55C in still air
1.0
W
TSTG
Storage temperature
-65
150
C
Pin Functions
Name
Number
Type
Description
CLK_IN
1
I
Reference Clock inptu, CLK_IN allows spread spectrum clock input
AVCC
2
Power
Analog Power
AGND
3
Ground
Analog Ground
CLK_OUT
4
O
Clock Output. The output provides low-skew copies of CLK_IN and has an embedded
series-damping resistor.
S5
I
Control Input S. S is used to bypass the PLL for test purposes. When S is strapped to
ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs
GND
6
Ground
VCC
7
Power
Power Supply
FB_IN
8
I
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Note:
1.
Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
08-0298
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