參數(shù)資料
型號(hào): PI6C185-02BQE
廠商: Pericom
文件頁(yè)數(shù): 5/6頁(yè)
文件大小: 0K
描述: IC CLK BUFFER 1:7 140MHZ 16-QSOP
標(biāo)準(zhǔn)包裝: 97
類(lèi)型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:7
差分 - 輸入:輸出: 無(wú)/無(wú)
輸入: TTL
輸出: TTL
頻率 - 最大: 140MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
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PS8469
05/03/00
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PI6C185-02B
Precision 1-7 Clock Buffer
1.5V
tphl
tplh
1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
tSDFALL
tSDRISE
Test Load
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500
resistor in parallel.
Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place RS series resistors and CI capacitors as close as possible to the respective clock pins. Typical
value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise
and fall time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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PI6C18551WEX 功能描述:時(shí)鐘緩沖器 3.3V/5V 1to 4 時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲(最大值): 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel