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參數(shù)資料
| 型號(hào)： | PI6C180VE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF 1:18 100MHZ 48-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Total Timing Technology |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:18 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 輸入： | TTL |
| 輸出： | TTL |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
3
PS8141F
12/13/04
PI6C180
Precision 1-18 Clock Buffer
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device’s
own address is detected, PI6C180 generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin
Description
7
45
SDRAM15 (Active/Inactive)
6
44
SDRAM14 (Active/Inactive)
5
41
SDRAM13 (Active/Inactive)
4
40
SDRAM12 (Active/Inactive)
3
36
SDRAM11 (Active/Inactive)
2
35
SDRAM10 (Active/Inactive)
1
32
SDRAM9 (Active/Inactive)
0
31
SDRAM8 (Active/Inactive)
Byte2: Optional Register for Possible Future Requirements
(1 = enable, 0 = disable)
Bit
Pin
Description
7
28
SDRAM17 (Active/Inactive)
6
21
SDRAM16 (Active/Inactive)
5
(Reserved)
4
(Reserved)
3
(Reserved)
2
(Reserved)
1
(Reserved)
0
(Reserved)
Storage Temperature........................................–65°C to +150°C
Ambient Temperature with Power Applied.........–0°C to +70°C
3.3V Supply Voltage to Ground Potential ..........–0.5V to +4.6V
DC Input Voltage ................................................–0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
reliability.
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol
Parameter
Test Condidtion
Min.
Typ.
Max.
Units
IDD
Supply Current
BUF_IN = 0 MHz
2
mA
IDD
BUF_IN = 66.66 MHz
230
IDD
BUF_IN = 100.00 MHz
360
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C180 is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
EverybiteputontheSDATAlinemustbe8-bitslong(MSBfirst),fol-
lowed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATAchanges only when SCLOCK
is LOW. Exceptions: AHIGH to LOW transition on SDATAwhile
SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATAwhile SCLOCK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
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