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參數(shù)資料
| 型號： | PI6C104S |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Spread Spectrum Clock Synthesizer for Desktop Pentium II |
| 中文描述： | 擴頻時鐘合成器為桌面奔騰II |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 560K |
| 代理商： | PI6C104S |
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PS8164B 03/15/99
PI6C104
Spread Spectrum Clock Synthesizer
PI6C104 I
2
C Address Assignment 0D2H
2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C104 is a slave receiver device. It can not be read back. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLK is HIGH indicates a start condition. A LOW to HIGH
transition on SDATA while SCLK is HIGH is a stop condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is always
a 7-bit address byte followed by a read/write bit. (HIGH = read
from addressed device, LOW = write to addressed device).
If the devices own address is detected, PI6C104 generates an
acknowledge by pulling SDATA line LOW during ninth clock
pulse, then accepts the following data bytes until another start or
stop condition is detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. Command Code byte, and
2. Byte Count byte.
Although the data bits on these two bytes are dont care, they
must be sent and acknowledged.
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Clock Enable Configuration
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