參數(shù)資料
型號: PI5A3159ZCEX
廠商: Pericom Semiconductor Corp.
英文描述: SOTINYTM 1з Low-Voltage SPDT Analog Switch
中文描述: SOTINYTM1з低電壓SPDT模擬開關(guān)
文件頁數(shù): 3/10頁
文件大?。?/td> 604K
代理商: PI5A3159ZCEX
3
PS8634C 09/13/04
PI5A3159
SOT
INY
TM
1 Low-Voltage
SPDT Analog Switch
Electrical Specifications - Single +5V Supply
(continued)
(V+ = + 5V ± 10%, GND = 0V, V
INH
= 2.4V, V
INL
= 0.8V)
Parameter
Symbol
Conditions
Temp(°C)
Min
(1)
Typ
(2)
Max
(1)
Units
Analog Switch
Input HIGH Voltage
Input LOW Voltage
Input Current with
HIGH Voltage
Input Current with LOW
Voltage
V
IH
V
IL
Guaranteed Logic HIGH level
Guaranteed Logic LOW level
V
0.8
I
INH
V
IN
= 2.4V, all others = 0.8V
-1
0.005
1
μA
I
INL
V
IN
= 0.8V, all others = 2.4V
-1
0.005
1
Dynamic
Turn-On-Time
t
ON
V
CC
= 5V,
See Fig. 1
25
Full
25
Full
25
Full
20
35
40
20
35
14.5
ns
Turn-Off-Time
t
OFF
15
Break-Before-Make
t
BBM
See Fig. 3
1
1
12
17.5
Charge Injection
(3)
Q
C
L
-1nF, V
GEN
= 0V,
R
GEN
= 0V, See Fig 2
R
L
= 50, f = 1MHz, See Fig 4
R
L
= 50, f = 1MHz, See Fig 4
f = 1MHz, See Fig 6
f = 1MHz, See Fig 6
f = 1MHz, See Fig 7
25
40
pC
Off Isolation
CrossTalk
(9)
NC or NO Capacitance
COM Off Capacitance
COM On Capacitance
O
IRR
X
TALK
C
NC/NO(OFF)
C
COM(OFF)
C
COM(ON)
-57
-57
42
83
130
dB
pF
Supply
Power-Supply Range
V+
Full
1.8
5.5
V
Positive Supply Current
1+
V+ = 5.5V, V
IN
= 0V or V+,
All Channels ON or OFF
Full
0.5
1
μA
Notes:
1. The algebraic convention, where most negative value is a minimum and most positive is a maximum, is used in this data sheet.
2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
3. Guaranteed by design.
4. Device is NOT guaranteed to function per the datasheet specification outside of 0 to V+ range.
5. ΔR
ON
=
R
ON
max. - R
ON
min.
6. Flatness is defined as the difference between the maximum and minimum value of On-resistance measured.
7. Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25oC.
8. Off Isolation = 20log
10
[ V
COM
/ (V
NO
or V
NC
)
]. See Figure 4.
9. Between any two switches. See Figure 5.
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