5.0Gbps 4-Lane PCIe 2.0 ReDdriver
參數(shù)資料
型號(hào): PI2EQX5864CZFE
廠商: Pericom
文件頁(yè)數(shù): 3/20頁(yè)
文件大小: 0K
描述: IC PCI-E REDRIVER 56TQFN
標(biāo)準(zhǔn)包裝: 66
系列: ReDriver™
類型: 轉(zhuǎn)接驅(qū)動(dòng)器
Tx/Rx類型: CML
電容 - 輸入: 50pF
電源電壓: 1.15 V ~ 1.25 V
電流 - 電源: 800mA
安裝類型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(5x11)
包裝: 管件
11
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe 2.0 ReDdriver
with Equalization, Emphasis and I2C Control
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
76543210
Name
PD_A0#
PD_B0#
PD_A1#
PD_B1#
PD_A2#
PD_B2#
PD_A3#
PD_B3#
Type
R/W
Power-on
State
11111111
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the
channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
76543210
Name
RXD_A0
RXD_B0
RXD_A1
RXD_B1
RXD_A2
RXD_B2
RXD_A3
RXD_B3
Type
R/W
Power-on
State
11111111
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When
RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is
enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer conguration, Dx_A: Emphasis control, Sx_A: Output level control (see Conguration Table)
Bit
76543210
Name
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Type
R/W
Power-on
State
11111111
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
BYTE 5 - Channel Reset (RESET)
RESET# =0=reset, RESET# =1=normal operation. Latch from RESET# input at startup
Bit
76543210
Name
RES_A0#
RES_B0#
RES_A1#
RES_B1#
RES_A2#
RES_B2#
RES_A3#
RES_B3#
Type
R/W
Power-on
State
11111111
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates a
new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RESET# bit will have
no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
09-0002
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