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參數(shù)資料
| 型號(hào)： | PI1004-1-QAHG |
| 廠(chǎng)商： | Vicor Corporation |
| 元件分類(lèi)： | DC/DC變換器 |
| 英文描述： | Programmable Point-of-Load Controller with 6-bit VID |
| 中文描述： | 可編程點(diǎn)負(fù)載控制器的6位VID |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 708K |
| 代理商： | PI1004-1-QAHG |
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Picor Corporation picorpower.com
PI1004 Data Sheet Rev. 2.5
Page 2 of 16
Pin Description
PIN #
1- 6
Pin Name
VID[0:5]
Description
Voltage identification digital inputs. The VID inputs program the reference voltage on the REFOUT
pin. Tying all VID pins high is treated as a fault and sets the fault latch. To hardwire the VID code, the
inputs may be connected to Vcc or SGND as applicable. See Table 1 for VID codes.
7
PWRGD
Power-good open-collector output. This pin is an open circuit when
(REFIN-230 mV)
≤
VO
≤
(REFIN+160
mV)
and the input bus voltage is not in a UVLO condition. When VO is outside the VO window,
(REFIN-
230 mV ) < VO < (REFIN+160 mV)
or the input bus voltage is in a UVLO condition, or if the ENABLE is
low, the PWRGD output is low.
8
OFFSET
PI1004-1 only. Provides a programmable VID offset current. A current equal to the current out of the
OFFSET pin is added to IAVP to provide a fixed negative offset. To program the offset connect a resistor
between OFFSET and SGND. The current is nominally equal to 0.25 V / ROFFSET. Not used tie to Vcc.
8
OVP
PI1004-2 only. Over-voltage protection signal, TTL output. When
VO
≥
(REFIN+220 mV)
and the input
bus voltage is not in a UVLO condition and ENABLE is high, OVP is high. When
VO < (REFIN+220 mV)
or the input bus voltage is in a UVLO condition, or ENABLE is low, OVP is low.
9
ENABLE
Logic input control of biasing. If ENABLE = low the PI1004 is disabled and quiescent current is reduced
to <400 uA. If ENABLE = high the PI1004 is enabled and the part operates normally if Vcc > UVLO.
10
SS
Soft start programming terminal. The error amp non-inverting input (EAIP) is clamped below the level
of the SS pin. An internal 5uA charging current is provided to program soft start with an external
capacitor. Soft start pin is discharged and held low with ENABLE low, UVLO, or VID=x11111. To control
soft-start connect a capacitor between the SS pin and SGND.
11
VO
Output voltage positive sense signal used for the power good and over-voltage protection circuits.
Connect directly to the output or if feedback divider is employed, connect to the output through a
voltage divider with the same ratio as the feedback divider.
12
ISN
Load current negative sense terminal. Connect ISN to the negative side of the sense resistor.
If AVP is not used, tie ISN to SGND.
13
ISP
Load current positive sense terminal. Connect ISP to the positive side of the sense resistor to detect
load current for AVP. If AVP is not used, tie ISP to SGND.
14
RG
Adaptive voltage positioning gain resistor connection. The sink current from the IAVP pin is:
IAVP = 4*[V(ISP)-V(ISN)]/RG. If AVP is not used, tie RG to Vcc.
15
IAVP
Adaptive voltage positioning sink current. This pin sinks current proportional to the load.
Connect to the EAIP pin with an AVP resistor (RAVP) tied from EAIP to REFOUT. The regulator
output voltage will drop with increasing load. If AVP is not used, connect IAVP to Vcc.
16
REFIN
Reference input voltage for the over-voltage protection and power good indicators.
Normally REFIN is tied to REFOUT.
17
EAIP
Non-inverting input to the error amplifier. If AVP and offset are not used, connect EAIP to
REFOUT. To use AVP connect directly to IAVP and to REFOUT through a resistor.
18
EAIN
Inverting input to the error amplifier. Connect EAIN to the positive remote output voltage sense
point through the feedback network. Run in parallel to the SGND connection to avoid noise pick-up.
19
EAO
Error amplifier output terminal.
20
REFOUT
Reference output voltage as defined by the VID codes in Table 1. The reference is capable of sourcing
up to 1 mA of current. In a typical CPU application REFOUT is connected to REFIN to set the thresholds
for Power Good and to EAIP through a resistor to enable Adaptive Voltage Positioning.
21
VCC
Internal circuit supply. Bypass Vcc to SGND with a 0.1 μF capacitor.
22
SGND
Internal substrate connection and negative output voltage sense terminal.
Connect to the negative remote output voltage sense point and run in parallel with the positive sense
line to avoid noise pick-up.
23,24
NC
No connect. Post package programming pin.
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