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參數(shù)資料
| 型號： | PHD50N03LT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管) |
| 中文描述： | 48 A, 25 V, 0.018 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC, DPAK-3 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 108K |
| 代理商： | PHD50N03LT |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHP50N03LT, PHB50N03LT
PHD50N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 25 V
’Trench’
technology
Very low on-state resistance
Fast switching
High thermal cycling performance
Low thermal resistance
Logic level compatible
I
D
= 48 A
R
DS(ON)
≤
16 m
(V
GS
= 10 V)
R
DS(ON)
≤
21 m
(V
GS
= 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’
trench
’ technology.
Applications:-
High frequency computer motherboard d.c. to d.c. converters
High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N03LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D
2
PAK)
SOT428 (DPAK)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage (DC)
V
GSM
Gate-source voltage (pulse
peak value)
I
D
Drain current (DC)
CONDITIONS
T
j
= 25 C to 175C
T
j
= 25 C to 175C; R
GS
= 20 k
MIN.
-
-
-
-
MAX.
25
25
±
15
±
20
UNIT
V
V
V
V
T
j
≤
150C
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
-
-
-
48
34
180
A
A
A
I
DM
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
P
tot
T
j
, T
stg
T
mb
= 25 C
-
86
175
W
C
- 55
d
g
s
1 2 3
tab
1
3
tab
2
1
2
3
tab
1
It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.800
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PHB50N03 | N-channel TrenchMOS transistor Logic level FET |
| PHB50N03T | TrenchMOS transistor Standard level FET |
| PHB50N06LT | TrenchMOS transistor Logic level FET |
| PHB50N06T | TrenchMOS transistor Standard level FET |
| PHB55N03LT | N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PHD50N06LT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TrenchMOS transistor Logic level FET |
| PHD55N03LT | 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:MOSFET Transistor, N-Channel, TO-252AA |
| PHD55N03LT/T3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR POWER MOSFET D-PAK |
| PHD55N03LTA | 制造商:NXP Semiconductors 功能描述:55 A, 25 V, 0.018 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252 |
| PHD55N03LTA,118 | 功能描述:MOSFET TAPE13 MOSFET RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
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