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參數(shù)資料
| 型號： | PGA102AG |
| 英文描述： | High Speed PROGRAMMABLE GAIN AMPLIFIER |
| 中文描述： | 高速可編程增益放大器 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 96K |
| 代理商： | PGA102AG |
PGA102
7
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the PGA102. Power supplies should be bypassed with
0.1
μ
F capacitors located close to the device pins.
The inputs for each gain are independent and can be con-
nected to three separate signal sources. Or, for many appli-
cations, the three inputs are connected in parallel to form a
single input—see Figure 1. Only the input corresponding to
the selected gain is active, operating as a non-inverting
amplifier. The two inactive inputs behave as open circuits.
The input bias current of the inactive inputs is negligible
compared to that of the selected input.
DIGITAL INPUTS
Gain is selected by the digital input pins, "X10" and “X100”.
The threshold of these logic inputs is approximately 1.3V
above the voltage on pin 3. For CMOS or TTL logic signals,
connect pin 3 to logic ground. The logic inputs are not
latched. Any change logic inputs immediately selects a new
gain. Switching time is approximately 1
μ
s. This does not
include the time required for the analog output to settle to a
new output value (see settling time specifications).
Note that the two logic inputs allow four possible logic
states—see Figure 1 for the logic table. A logic “1” on both
inputs is an invalid code. This will not damage the device,
but the analog output voltage will not be predictable while
this code is applied.
FIGURE 1. Basic Circuit Connections.
OFFSET ADJUSTMENT
The offset voltage of each of the three input stages is laser-
trimmed. Many applications require no further adjustment.
The optional trim circuit shown in Figure 1 can be used to
adjust the offset voltage. This adjustment affects the offset
of all three gain channels. Since each gain setting may
require a different adjustment of the potentiometer, this
requires a compromise. Often, offset voltage of the G = 100
channel is the most important, so adjustment can be opti-
mized for this channel only. Alternatively, Figure 2 shows a
CMOS switch used to select independent offset adjustment
potentiometers for each of the three channels.
Use these offset adjustment techniques only to null the offset
voltage of the PGA102. Do not null offset produced by the
signal source or other system offsets or this will increase the
temperature drift of the PGA102.
FIGURE 2. Independent Offset Adjustment of Channels 1, 2,
and 3.
GAIN ADJUSTMENT
Gain of the PGA102 is accurately laser trimmed and usually
requires no further adjustment. The optional circuit in
Figure 3 allows independent gain adjustment of the G = 10
and G = 100 inputs.
1
15
2
3
4
5
V
O
Digital
Ground
–V
CC
12
6
Output
Ground
Analog
Ground
0.1μF
0.1μF
–V
CC
+V
CC
Optional
Offset
Trim
13
16
11
V
IN1
7
V
IN2
8
V
IN3
Input
Ground
INPUT
V
IN1
V
IN2
V
IN3
— Invalid —
GAIN
G = 1
G = 10
G = 100
X10
0
1
0
1
X100
0
0
1
1
Logic “0”: 0V
≤
V
≤
0.8V
Logic “1”: 2V
≤
V
≤
+V
CC
Logic voltages are referred to pin 3.
100k
1
15
3
Adjust for
V
= 0V
for all channels.
6
–15V
13
16
7
8
V
IN
= 0V
211
45
12
+15V
R
1
100k
R
2
100k
R
3
100k
14 11 12 7
2
3
9
–V
CC
+15V
PGA102
1
4
8
CH1
CH2
CH3
6
5
13
CH1CH2CH3
0
0
1
0
1
0
1
0
0
A
B
C
CH1
CH2
CH3
Offset
Adjusts
4016
CMOS
SWITCH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PGA102BG | High Speed PROGRAMMABLE GAIN AMPLIFIER |
| PGA102KP | High Speed PROGRAMMABLE GAIN AMPLIFIER |
| PGA102SG | High Speed PROGRAMMABLE GAIN AMPLIFIER |
| PGA103 | Programmable Gain AMPLIFIER |
| PGA103P | KPT02A18-11PX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PGA102AG-BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Instrumentation Amp， Pin-Programmable |
| PGA102BG | 制造商:BB 制造商全稱:BB 功能描述:High Speed PROGRAMMABLE GAIN AMPLIFIER |
| PGA102BG-BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Instrumentation Amp， Pin-Programmable |
| PGA102KP | 制造商:BURR-BROWN CORPORATION 功能描述:Electronic Instrumentation Amplifier, Single, 16 Pin, Plastic, DIP |
| PGA102KP-BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Instrumentation Amp， Pin-Programmable |
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