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參數(shù)資料
| 型號： | PF38F1020WYTQ1 |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, SCSP-88 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 364K |
| 代理商： | PF38F1020WYTQ1 |
32-Mbit W18 + 8-Mbit SRAM (38F1020W0YTQ1, 38F1020W0YBQ1)
28 Jun 2005
Intel StrataFlash Wireless Memory (W18 SCSP)
Datasheet
18
Order Number: 252635, Revision: 003
9.0
Device Operation
Bus operations for the 38F1020W0YQ1 devices involve the control of the flash and SRAM inputs.
The chip enable (CE#1) and output enable (OE#1) control the flash memory device.
Table 6 shows the flash memory and SRAM bus operations.
Refer to the Intel Wireless Flash Memory (W18) Datasheet for complete descriptions of flash
memory modes and commands, and for command bus-cycle definitions and flowcharts for
operational routines.
10.0
Flash Memory Read Operations
For detailed information about reads from the flash memory device, refer to the Intel
Wireless
Flash Memory (W18) Datasheet.
Table 6.
Bus Operations
De
v
ic
e
Mode
RS
T
#
CE
#
1
OE
#
1
WE
#
VP
P
WA
IT
S-C
S
1
#
S-
C
S
2
R-OE
#
R-W
E
#
R-UB#
,
R-
L
B
#
D[1
5
:0
]
No
te
s
a
s
h
M
e
m
o
ry
Read
H
L
H
X
Valid/
Driven
SRAM must be in High-Z
Flash Memory
DOUT
1,2,3,5,6
Write
H
L
H
L
VPP1 or
VPP2
Driven
Flash Memory
DIN
3,4,7
Output
Disable
HL
H
X
Driven
Any SRAM mode allowed
Flash Memory
High-Z
5
Standby
H
X
High-Z
Flash Memory
High-Z
5
Reset
L
X
High-Z
Flash Memory
High-Z
5
S
RAM
Read
Flash device must be in High-Z
Note 2
L
H
L
H
L
SRAM DOUT
1,4
Write
Note 2
L
H
L
SRAM DIN
4
Output
Disable
Any flash device mode allowed
Note 2
L
H
X
SRAM High-Z
5
Standby
Note 2
H / X
X / L
X
SRAM High-Z
5,8
Data
Retention
Note 2
Same as SRAM standby
SRAM High-Z
9
Notes:
1.
For asynchronous read operation, both die can be simultaneously selected, but both die cannot simultaneously drive
the memory bus. For synchronous burst-mode reads, both die can be simultaneously selected.
2.
WAIT is valid during synchronous flash memory reads. WAIT is driven if CE#1 is asserted.
3.
Do not simultaneously assert OE#1 and WE#.
4.
For SRAM, do not simultaneously assert R-OE#1 and R-WE#.
5.
X can be VIL or VIH for inputs, VPP1, VPP2 or VPPLK for VPP.
6.
Flash CFI query and status register accesses use D[7:0] only; all other reads use D[15:0].
7.
Refer to
the Intel Wireless Flash Memory (W18) Datasheet for valid DIN during flash memory writes.
8.
The SRAM is enabled or disabled using the following logical function: S-CS1# OR S-CS2.
9.
To place the SRAM into data retention mode, lower S-VCC to the VDR limit when in standby mode.
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