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參數(shù)資料
| 型號(hào)： | Pentium OverDrive Processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器) |
| 中文描述： | 奔騰過驅(qū)動(dòng)處理器的MMX技術(shù)的Pentium處理器為基礎(chǔ)的系統(tǒng)（帶MMX公司技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器） |
| 文件頁數(shù)： | 20/61頁 |
| 文件大?。?/td> | 481K |
| 代理商： | PENTIUM OVERDRIVE PROCESSOR |
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Pentium
OverDrive
PROCESSOR WITH MMX
TECHNOLOGY
E
20
9/8/97 11:55 AM 29060701.DOC
PRELIMINARY
Table 2. Quick Pin Reference
Symbol
Type
Name and Function
RESET
I
RESET
forces the Pentium OverDrive processor with MMX technology to begin
execution at a known state. All Pentium OverDrive processor internal caches
written back. FLUSH#, and INIT are sampled when RESET transitions from high
to low to determine if tristate test mode mode will be entered, or if BIST will be
run.
SCYC
O
The
split cycle
output is asserted during misaligned LOCKed transfers to
indicate that more than two cycles will be locked together. This signal is defined
for locked cycles only. It is undefined for cycles which are not locked.
SMI#
I
The
system management interrupt
causes a system management interrupt
request to be latched internally. When the latched SMI# is recognized on an
instruction boundary, the processor enters System Management Mode.
SMIACT#
O
An active
system management interrupt active
output indicates that the
processor is operating in System Management Mode (SMM).
STPCLK#
I
Assertion of the
stop clock
input signifies a request to stop the internal clock of
the Pentium OverDrive processor with MMX technology thereby causing the
core to consume less power. When the CPU recognizes STPCLK#, the
processor will stop execution on the next instruction boundary, unless
superseded by a higher priority interrupt, and generate a stop grant
acknowledge cycle. When STPCLK# is asserted, the Pentium OverDrive
processor with MMX technology will still respond to external snoop requests.
TCK
I
The
testability clock
input provides the clocking function for Pentium OverDrive
processor with MMX technology boundary scan in accordance with the IEEE
Boundary Scan interface (Standard 1149.1). It is used to clock state information
and data into and out of the Pentium OverDrive processor with MMX technology
during boundary scan.
TDI
I
The
test data input
is a serial input for the test logic. TAP instructions and data
are shifted into the Pentium OverDrive processor with MMX technology on the
TDI pin on the rising edge of TCK when the TAP controller is in an appropriate
state.
TDO
O
The
test data output
is a serial output of the test logic. TAP instructions and
data are shifted out of Pentium OverDrive processor with MMX technology on
the TDO pin on TCK’s falling edge when the TAP controller is in an appropriate
state.
TMS
I
The value of the test mode select input signal sampled at the rising edge of TCK
controls the sequence of TAP controller state changes.
TRST#
I
When asserted, the
test reset
input allows the TAP controller to be
asynchronously initialized.
V
CC2
I
These 28
power
inputs are defined separately so they may be used in a split
voltage plane motherboard design. These pins
must
be supplied with 3.3V for
the Pentium OverDrive processor with MMX technology to function.
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