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| 型號： | pentium III CPU |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| 中文描述： | 奔騰III處理器在450MHz至1.0GHz的（SC242工作頻率至450MHz到1GHz的奔三處理器的SC242） |
| 文件頁數(shù)： | 94/102頁 |
| 文件大?。?/td> | 920K |
| 代理商： | PENTIUM III CPU |
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94
Datasheet
Pentium
III Processor for the SC242 at 450 MHz to 1.0 GHz
7.0
Intel
Pentium
III Processor Signal Description
This section provides an alphabetical listing of all Intel
Pentium
III
processor signals. The tables
at the end of this section summarize the signals by direction: output, input, and I/O.
7.1
Alphabetical Signals Reference
Table 41. Signal Description
(Sheet 1 of 7)
Name
Type
Description
A[35:3]#
I/O
The A[35:3]# (Address) signals define a 2
36
-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
pins to determine their power-on configuration. See the Pentium
II Processor
Developer’s Manual(Order Number 243502) for details.
A20M#
I
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of
A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
ADS#
I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all processor system bus agents.
AERR#
I/O
The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate pins on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.
AP[1:0]#
I/O
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are
low and low if an odd number of covered signals are low. This allows parity to be
high when all the covered signals are high. AP[1:0]# should connect the appropriate
pins of all processor system bus agents.
BCLK
I
The BCLK (Bus Clock) signal determines the bus frequency. All processor system
bus agents must receive this signal to drive their outputs and latch their inputs on
the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
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