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| 型號(hào)： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 94/97頁 |
| 文件大小： | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
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12/15/98 5:14 PM 24377002.doc
accepting
processors save the current state and enter System
Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins
program execution from the SMM handler.
a
System
Management
Interrupt,
9.1.49.
STPCLK# (I)
The STPCLK# (Stop Clock) signal, when asserted,
causes processors to enter a low power Stop Grant
state. The processor issues a Stop
Acknowledge transaction, and stops providing
internal clock signals to all processor core units
except the bus and APIC units. The processor
continues to snoop bus transactions and service
interrupts while in Stop Grant state. When STPCLK#
is deasserted, the processor restarts its internal
clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
Grant
9.1.50.
TCK (I)
The TCK (Test Clock) signal provides the clock input
for the Pentium II Xeon processor Test Bus (also
known as the Test Access Port).
9.1.51.
TDI (I)
The TDI (Test Data In) signal transfers serial test
data into the Pentium II Xeon processor. TDI
provides the serial input needed for TAP support.
9.1.52.
TDO (O)
The TDO (Test Data Out) signal transfers serial test
data out of the Pentium II Xeon processor. TDO
provides the serial output needed for TAP support.
9.1.53.
TEST_25_A62 (I)
The TEST_25_A62 signal must be connected to a
2.5 V power source through a 1-10k
resistor for
proper processor operation.
9.1.54.
TEST_VCC_CORE_XXX (I)
The TEST_VCC_CORE_XXX signals must be
connected separately to V
CCCORE
via ~10K resistors.
9.1.55.
THERMTRIP# (O)
This pin indicates a thermal overload condition
(thermal trip). The processor protects itself from
catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there
are no false trips. The processor will immediately
stop all execution when the junction temperature
exceeds approximately 135 °C. This is signaled to
the system by the THERMTRIP# pin. Once
activated, the signal remains latched, and the
processor stopped, until RESET# goes active. There
is no hysteresis built into the thermal sensor itself.
Once the die temperature drops below the trip level,
a RESET# pulse will reinitialize the processor and
execution will continue at the reset vector. If the
temperature has not dropped below the trip level, the
processor will continue to drive THERMTRIP# and
remain stopped regardless of the state of RESET#.
9.1.56.
TMS (I)
The TMS (Test Mode Select) signal is a TAP support
signal used by debug tools.
9.1.57.
TRDY# (I)
The TRDY# (Target Ready) signal is asserted by the
target to indicate that it is ready to receive a write or
implicit writeback data transfer. TRDY# must connect
the appropriate pins of all Pentium II Xeon processor
system bus agents.
9.1.58.
TRST# (I)
The TRST# (Test Reset) signal resets the Test
Access Port (TAP) logic. Pentium II Xeon processors
self-reset during power on; therefore, it is not
necessary to drive this signal during power on reset.
9.1.59.
VID_L2[4:0], VID_CORE[4:0](O)
The VID (Voltage ID) pins can be used to support
automatic selection of power supply voltages. These
pins are not signals, but are either an open circuit or
a short circuit to V
SS
on the processor. The
combination of opens and shorts defines the voltage
required by the processor. The VID pins are needed
to cleanly support voltage specification variations on
Pentium II Xeon processors. See Table 2 for
definitions of these pins. The power supply must
supply the voltage that is requested by these pins, or
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