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參數(shù)資料
| 型號： | PEEL18CV8P-25 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Programmable Electrically Erasable Logic Device |
| 中文描述： | 的CMOS電可擦除可編程邏輯器件 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 411K |
| 代理商： | PEEL18CV8P-25 |
4
04-02-004H
International
CMOS
Technology
PEEL
TM
18CV8
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
The PEEL18CV8 macrocell also provides control over the
feedback path. The input/feedback signal associated with
each I/O macrocell may be obtained from three different
locations; from the I/O input pin, from the Q output of the
flip-flop (registered feedback), or directly from the OR gate
(combinatorial feedback).
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output func-
tion with a bi-directional I/O.)
Combinatorial Feedback
The signal-select multiplexer gives the macrocell the ability
to feedback the output of the OR gate, bypassing the out-
put buffer, regardless of whether the output function is reg-
istered or combinatorial. This feature allows the creation of
asynchronous latches, even when the output must be dis-
abled. (Refer to configurations 5,6,7 and 8 in Figure 5.)
Figure 4 Block Diagram of the PEEL18CV8
I/O Macrocell
Registered Feedback
Feedback also can be taken from the register, regardless of
whether the output function is to be combinatorial or regis-
tered. When implementing a combinatorial output function,
registered feedback allows for the internal latching of states
without giving up the use of the external output.
Design Security
The PEEL18CV8 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the conclusion of the program-
ming cycle or as a separate step, after the device has been
programmed. Once the security bit is set it is impossible to
verify (read) or program the PEEL until the entire device
has first been erased with the bulk-erase function.
Programming Support
ICT’s JEDEC file translator allows easy conversion of exist-
ing 20 pin PLD designs to the PEEL18CV8, without the
need for redesign. ICT supports a broad range of popular
third party design entry systems, including Data I/O Synario
and Abel, Logical Devices CUPL and others. ICT also
offers (for free) its proprietary PLACE software, an easy-to-
use entry level PC-based software development system.
Programming support includes all the popular third party
programmers; Data I/O, Logical Devices, and numerous
others. ICT also provides a low cost development program-
mer system, the PDS-3.
相關(guān)PDF資料 |
PDF描述 |
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| PEEL18CV8P-7 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL18CV8J-10 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL18CV8J-15 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL18CV8TI-10 | CMOS Programmable Electrically Erasable Logic Device |
| PEEL18CV8TI-15 | CMOS Programmable Electrically Erasable Logic Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEEL18CV8P-25L | 功能描述:SPLD - 簡單可編程邏輯器件 10 INP 8 I/O 25ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PEEL18CV8P-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| PEEL18CV8P-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| PEEL18CV8P-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Programmable Electrically Erasable Logic Device |
| PEEL18CV8P50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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