
AN-SETS-5
PECL Driver
ADVANCED COMMUNICATIONS
APPLICATION NOTE
Revision 2.0/August 2001 Semtech Corp.
Page 4
www.semtech.com
4
Possible Solutions
Since the PECL outputs on the SETS chips are differential, the implications of this level shift should be minor as long
as the receiving stage can accommodate a slightly lower than standard common mode input voltage. For example the
SETS PECL receivers can have an input common mode range anywhere between 0V and VDD and as long as the
differential input swing is greater than 200mV the signal will be correctly received.
However, if it is essential that the receiving stage sees a higher common mode switching point then this can be
achieved albeit at the expense either of reduced signal amplitude or reduced bandwidth
The normal PECL termination is 50ohm to VDD-2V. If the impedance is increased then the Voh levels will increase since
there is less pull down current on the NMOS output transistor. However to achieve a significantly higher Voh would
require a load impedance of around 500ohm which would drastically reduce bandwidth although the signal swing
would be essentially unchanged.
A possible compromise is to increase the load impedance by a smaller factor but also increase the effective
termination voltage to a value higher than VDD-2V.
The following plot shows operation at 155MHz with a 100ohm termination to VDD-1.4V. For VDD=3.3V this can be
achieved by a 180ohm resistor from VDD to the output and a 240ohm resistor from the output to Ground.
Figure 4.1
Voltage/Time plot at 155MHz (worst case), 100ohm termination on VDD-1.4V
As can be seen, the Voh level has now improved from VDD-1.25V to VDD-1.05V and the bandwidth has been
maintained, however the signal amplitude has now decreased from around 600mV to 250mV. For different receivers
and operating speeds there will be different optimum terminations and these can be determined on a case by case
basis.