參數(shù)資料
型號: PEB24901H
英文描述: LTC3026 Evaluation Kit
中文描述: ?四整體數(shù)位服務網(wǎng)路Echocancellation電路數(shù)字前端4B3T線路碼的終結?
文件頁數(shù): 61/73頁
文件大?。?/td> 1618K
代理商: PEB24901H
PEB 2466
PEF 2466
Electrical Characteristics and Timing Diagrams
Hardware Reference Manual
52
2001-02-20
8.8
Signaling Interface Timing
8.8.1
Timing from the
μ
C Interface to the SO/SB-pins
Figure 32
Signaling Output Timing (data downstream)
8.8.2
Timing from the SI/SB-pins to the
μ
C Interface
The register update and interrupt behavior resulting from signaling input changes (data
upstream
pins SI and SB, if programmed as signaling inputs) depend on internal
sampling clocks, counters and register settings. See
Chapter 5.3.2
for a functional
description.
Parameter
Symbol
Limit Values
typ.
Unit
min.
30
40
40
max.
t
dSout_min
+ t
C_Load
100
t
dSBD_min
+ t
C_Load
SO/SB delay time
1)
SB to
Z
- time
SB to
drive
-time
1)
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing,
and a second component t
C_Load
= 0.4ns*C
Load
/pF, caused by external circuitry (C-load).
t
dSout
t
dSBZ
t
dSBD
ns
ns
ns
DCLK
Bit 2
DIN
SO/SB Output
Old Value
New Value
SB
(Output
Input)
Output)
(Input
SB
dSBD
t
High Imp.
t
dSBZ
t
dSout
High Imp.
Bit 1
Bit 0
2466_232
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