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參數(shù)資料
| 型號： | PE7320DV-FREQ |
| 廠商： | PLETRONICS INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 40 MHz - 250 MHz, PECL OUTPUT |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 121K |
| 代理商： | PE7320DV-FREQ |
Differential PECL Series
Differential PECL Output, Some with Enable/ Disable Function
Standard Specifications
Overall Frequency Stability
Operating Temperature Range
0 to +80°C is standard, but can be extended to
Storage Temperature Range
- 55 to +125°C
- 40 to +85°C
Mechanical: See Next Pages
Supply Voltage (Vcc)
3.3 volts ± 5% standard, but 5.0 volts or 2.5 volts also available. See Test Cirucit 5.
E/D Internal Pullup
50 kohm minimum to Vcc
All other models Output Enable/Disable (E/D)
Output Enable Time
Output Disable Time
When Disabled
Output Symmetry
45/55% referenced to 50% of amplitude
Output Rise & Fall (Tr & Tf)
1.0 nS maximum when Vth is 10% and 90% of waveform
< 250 MHz = 90 mA maximum, 250 MHz and above = 100 mA maximum
Supply Current (Icc)
2.275 V minimum referenced to Ground, Vcc = 3.300V,
0.975 V minimum referenced to termination voltage,
- 1.025 V minimum referenced to Vcc
Output High Level
1.680 V maximum referenced to Ground, Vcc = 3.300V,
0.380 V maximum referenced to termination voltage,
- 1.620 V maximum referenced to Vcc
Output Low Level
1 pS RMS maximum measured from 12 kHz to 20 MHz from Fnominal
Jitter
V enable
0.7 Vcc minumum referenced to Ground
0.3 Vcc maximum referenced to Ground
V disable
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
1
Pl tronics, Inc.
100 nS maximum
Output Disable Time
Q Output = Logic Low, QN Output = Logic High. Both Outputs are active
PE7745D only Output Enable / Disable
± 50 PPM, ± 25 PPM, ± 20 PPM over Operating Temperature Range
Available in 9 Different Package/Configurations, See Next Pages
D Package
J Package Replacement
B Package
M Package
Note 1:
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
PECL,
LVDS,
OCXO
Page
1
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7
Mar 2004
PECL and ECL are identical circuits.
ECL has the most positive pin as ground and is ideally terminated by 50 ohms to - 2.00 V
PECL has the most negative pin as ground and is ideally terminated by 50 ohms to the most (positive voltage less 2.00 V)
Output Enable Time
200 nS maximum at output enable or 1 mS maximum at output enabled and stable
High Level Input Current
Low Level Input Current
-20 uA maximum at Enable / Disable Pin = 0.7 Vcc
-200 uA maximum at Enable / Disable Pin = 0 V
200 nS maximum at output disable
Output Disable Time
Vcc Supply Current disabled < 1 mA. Both outputs are high impedance when disabled.
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