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參數(shù)資料
| 型號： | PE3320BVEF-FREQ |
| 廠商： | PLETRONICS INC |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 1.5 MHz - 180 MHz, PECL OUTPUT |
| 封裝： | LEADLESS PACKAGE-6 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 72K |
| 代理商： | PE3320BVEF-FREQ |
Mar 2004
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com
6A
Pl tronics, Inc.
PECL and LVDS Layout Guidelines Continued
Pl tronics, Inc.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA
Manufacturer of High Quality Frequency Control Products
.
Vcc
Vcc - 2.00 V
GND
Out
Vcc
Oscillator
Vcc
GND
Out
Vcc
Oscillator
PECL Terminations:
LVDS Terminations:
Mixed System Power Supply:
50 ohm
Vcc
GND
Out
Vcc
Oscillator
R load
Vcc
GND
Q Out
QN Out
Vcc
Oscillator
100 ohm
R1
R2
Suggested Terminations for 50 ohm impedance matched termination
Simple termination for NON impedance matched termination
Vcc
5.0 V
3.3 V
2.5 V
R1
82 ohm
130 ohm
249 ohm
Vcc
5.0 V
3.3 V
2.5 V
R load
274 ohm
147 ohm
86.6 ohm
R2
130 ohm
82 ohm
61.9 ohm
Thevenin Equivalent Termination
Design PCB traces for 50 ohm characteristic impedance
To use multiple supply voltages requires level translation. Direct circuit connection is not valid.
Mixed supply voltages are allowed. No translation is necessary. (ECL is returned to the most positive
supply and this is common to all circuits)
Mixed supply voltages are allowed. LVDS signal levels are power supply independent.
3.3 V LVDS oscillators properly interface 2.5 V Logic Arrays for example.
PECL
ECL
LVDS
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