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參數(shù)資料
| 型號： | PDU15FSERIES |
| 英文描述： | 5-BIT PROGRAMMABLE DELAY LINE |
| 中文描述： | 5位可編程延遲線 |
| 文件頁數(shù)： | 5/5頁 |
| 文件大?。?/td> | 81K |
| 代理商： | PDU15FSERIES |
PDU15F
Doc #97003
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
1 FAST-TTL Gate
5pf
±
10%
1.5V (Rising & Falling)
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PW
IN
= 1.5 x Total Delay
PER
IN
= 4.5 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
OUT
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
Timing Diagram For Testing
TD
AR
TD
AF
PER
IN
PW
IN
T
RISE
T
FALL
0.6V
0.6V
2.4V
1.5V
1.5V
1.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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