- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367883 > PDU15F-8M Delay Line PDF資料下載
參數(shù)資料
| 型號： | PDU15F-8M |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 81K |
| 代理商： | PDU15F-8M |
PDU15F
Doc #97003
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
5-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU15F)
FEATURES
PACKAGES
Digitally programmable in 32 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
Fits standard 24-pin DIP socket
Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU15F-series device is a 5-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A4-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance:
5% or 1ns,
whichever is greater
Inherent delay (TD
0
):
9ns typical (OUT)
8ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (T
AIS
):
Disable to output delay (T
DISO
):
6ns typ. (OUT)
Operating temperature:
0
°
to 70
°
C
Temperature coefficient:
100PPM/
°
C (excludes TD
0
)
Supply voltage V
CC
:
5VDC
±
5%
Supply current:
I
CCH
= 74ma
I
CCL
= 30ma
Minimum pulse width:
10% of total delay
5ns
1997 Data Delay Devices
data
delay
devices,
inc.
3
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
OUT/
OUT
EN/
GND
N/C
IN
N/C
GND
N/C
N/C
EN/
GND
VCC
A0
A1
A2
VCC
N/C
N/C
N/C
VCC
A3
A4
N/C
PDU15F-xx
DIP
PDU15F-xxA4
Gull-Wing
PDU15F-xxB4
J-Lead
PDU15F-xxM
Military DIP
PDU15F-xxMC4
Military Gull-Wing
PIN DESCRIPTIONS
IN
OUT
OUT/ Inverted Output
A0-A4 Address Bits
EN/
Output Enable
VCC
+5 Volts
GND
Ground
Delay Line Input
Non-inverted Output
DASH NUMBER SPECIFICATIONS
Part
Number
PDU15F-.5
PDU15F-1
PDU15F-2
PDU15F-3
PDU15F-4
PDU15F-5
PDU15F-6
PDU15F-8
PDU15F-10
PDU15F-12
PDU15F-15
PDU15F-20
Incremental Delay
Per Step (ns)
.5
±
.3
1
±
.5
2
±
.5
3
±
1.0
4
±
1.0
5
±
1.0
6
±
1.0
8
±
1.0
10
±
1.5
12
±
1.5
15
±
1.5
20
±
2.0
Total Delay
Change (ns)
15.5
±
1.0
31
±
1.6
62
±
3.1
93
±
4.7
124
±
6.2
155
±
7.8
186
±
9.3
248
±
12.4
310
±
15.5
372
±
18.6
465
±
23.3
620
±
31.0
NOTE: Any dash number between .5 and 20 not
shown is also available.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關PDF資料 |
PDF描述 |
|---|---|
| PDU15F-8MC4 | Delay Line |
| PDU15FSERIES | 5-BIT PROGRAMMABLE DELAY LINE |
| PDU16F-2A4 | 6-BIT PROGRAMMABLE DELAY LINE (SERIES PDU16F) |
| PDU16F-.5 | 6-BIT PROGRAMMABLE DELAY LINE (SERIES PDU16F) |
| PDU16F-.5A4 | 6-BIT PROGRAMMABLE DELAY LINE (SERIES PDU16F) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDU15F-8MC4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| PDU15FSERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-BIT PROGRAMMABLE DELAY LINE |
| PDU15M2F10R | 制造商:Cyberpower Systems 功能描述:Rack Mount Metered Power Strip 2 Front 10 Rear Outlets 15A |
| PDU15M2F12R | 制造商:Cyberpower Systems 功能描述:Rack Mount Metered Power Strip 2 Front 12 Rear Outlets 15A |
| PDU15M2F8R | 制造商:Cyberpower Systems 功能描述:Rack Mount Metered Power Strip 2 Front 8 Rear Outlets 15A |
發(fā)布緊急采購，3分鐘左右您將得到回復。