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參數(shù)資料
| 型號： | PDSP16520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 32K BUCKET BUFFER |
| 中文描述： | 32K的鏟斗緩沖區(qū) |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 302K |
| 代理商： | PDSP16520 |
PDSP16540
3
FUNCTIONAL DESCRIPTION
D7
D8
D10
D12
D14
VDD
D17
GND
D19
D21
D23
D25
D26
D6
D9
D11
D13
D15
D16
D18
D20
D22
D24
D27
D4
D5
D28
D29
D2
D3
D30
D31
D0
D1
MD0
MD1
GND
RMF
MD2
GND
RS
WEN
MD3
MD4
VDD
DAV
MD5
VDD
WS
IP
0
IP
31
RES
IP
1
IP
2
IP
29
IP
30
IP
3
IP
4
IP
27
IP
28
IP
5
IP
8
IP
10
IP
12
IP
14
IP
16
IP
17
IP
19
IP
21
IP
23
IP
26
IP
6
IP
7
IP
9
IP
11
IP
13
VDD
IP
15
GND
IP
18
IP
20
IP
22
IP
24
IP
25
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
G
H
J
K
L
M
N
Pin Out Diagram - Bottom View (84pin PGA - AC84)
The PDSP16540 is designed for use in synchronous data
flow systems in which the transfer between system elements
is contolled by a continuously available system clock. This
system clock is usually at the maximum rate that the system
elements will allow, since it is governing the rate at which
processing can be performed on the acquired data. The rate
at which external data is actually inputed to the system ( the
sampling rate in DSP terminology ) is usually much slower
than the internal system, or computational, rate. The
PDSP16540 then provides a reservoir for data which is
acquired at the sampling rate and then processed with the
higher speed system clock rate.
Data is written to the RAM using an asynchronous write
strobe when a write enable input is active. The enbling signal
must meet the set up and hold times given in Table 1. Data is
read from the RAM using a read strobe which is expected to
be continuously availble and not to just go active when read
operations are actually needed. It is normally the high speed
system clock discussed earlier. All RAM addresses are
generated internally since the device is partitioning consecu-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDSP16488AC0 | Single Chip 2D Convolver with Integral Line Delays |
| PDSP16488AAC | Single Chip 2D Convolver with Integral Line Delays |
| PDSP16488AACBR | Single Chip 2D Convolver with Integral Line Delays |
| PDSP16488AB0 | Single Chip 2D Convolver with Integral Line Delays |
| PDSP16488AGC | Single Chip 2D Convolver with Integral Line Delays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16540 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32K BUCKET BUFFER |
| PDSP16540A0GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|QFL|132PIN|PLASTIC |
| PDSP16540B0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|PGA|84PIN|PLASTIC |
| PDSP16540B0GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|QFL|132PIN|PLASTIC |
| PDSP16540C0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MISC MEMORY|PGA|84PIN|PLASTIC |
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