參數(shù)資料
型號: PDSP16488A
廠商: Mitel Networks Corporation
英文描述: Single Chip 2D Convolver with Integral Line Delays(單片2D環(huán)繞的圖象處理設(shè)備(帶集成延遲線))
中文描述: 二維卷積器的單芯片線時滯的積分(單片二維環(huán)繞的圖象處理設(shè)備(帶集成延遲線))
文件頁數(shù): 18/33頁
文件大?。?/td> 412K
代理商: PDSP16488A
18
Switching Characteristics for Host mode
DS
hold time after
REPLY
low
Host address/data setup time
Read setup time to prevent Write
Host signal hold time
Expansion in to data out in
PROG
mode
Delay from
DS
low to
PC1
low (Note 2)
CE
setup time
CE
hold time
PROG
setup time
PROG
hold time
PC1
high delay after
DS
high
Coefficient read time
Coefficients valid time before
REPLY
Only applicable for Read ops and if
REPLY
is used
Only applicable if
REPLY
is used (Note 1)
Must always be guaranteed
No clocks are needed in
PROG
mode
Greater than
t
DEL
under all conditions
Defines
DS
high time
From Master or Single device
Conditions
Characteristic
Value
Min.
20
0
5
10
0
0
0
0
5
Symbol
Max.
30
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
t
DSH
t
HSU
t
RA
t
HH
t
DEL
t
EXP
t
CSU
t
CH
t
PSU
t
PH
t
PCH
t
ACC
t
RSU
DS
DATUM
t
CSU
t
CH
t
WAIT
>
t
PCH
t
PSU
t
PH
t
ACC
t
EXP
t
RSU
t
PCH
t
DSH
t
RA
t
HSU
t
DEL
t
HH
VALID
VALID
CE
PROG
COEFFICIENT OUTPUT, X7:0
PC1 FROM MASTER OR SINGLE DEVICE
PC1 FROM LAST DEVICE (REPLY)
R/W FROM HOST
ADDRESS/DATA FROM HOST
HOST DATA OUTPUT FROM FIRST DEVICE
Fig. 10 Host timing
NOTES
1. If REPLY is not used, time is referenced to the rising edge of DS and when set up must be N
3
t
DEL
for N devices.
2. Equivalent to PC0 to PC1 delay
相關(guān)PDF資料
PDF描述
PDSP16488AMAACBR JT 15C 14#20 1#16 PIN WALL REC
PDSP16488AMAGCPR Single Chip 2D Convolver with Integral Line Delays
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PDSP16488B0 Single Chip 2D Convolver with Integral Line Delays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDSP16488A0 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Single Chip 2D Convolver with Integral Line Delays
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