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參數(shù)資料
| 型號： | PDSP16318 MC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Complex Accumulator(復雜累加器（由兩個獨立的20位加法器/減法器組成）) |
| 中文描述： | 復雜累加器（復雜累加器（由兩個獨立的20位加法器/減法器組成）） |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 123K |
| 代理商： | PDSP16318 MC |
PDSP16318 MC
6
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
T
amb
(Military) =-55
°
C to +125
°
C, V
CC
= 5.0V
±
10%, GND = 0V
STATIC CHARACTERISTICS
Value
Characteristic
Symbol
Units
Max.
Conditions
Min.
Typ.
*
*
*
*
Output high voltage
Output low voltage
Input high voltage
Input low voltage
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I
IL
l
oz
I
OS
C
IN
2.4
-
2.0
-
-
0.4
-
0.8
-
0.5
+10
+50
200
-
V
V
V
V
V
V
μ
A
μ
A
mA
pF
I
OH
= 3.2mA
l
OL
=-3.2mA
Vdd - 1
-
-10
-50
20
-
CLK, CEA, CEB, OEC, OED
CLK, CEA, CEB, OEC, OED
GND < V
IN
<V
CC
GND <V
IN
< V
CC
V
cc
= Max
*
*
Input leakage current
Output leakage current
Output SC current
Input capacitance
-
-
9
Conditions
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
V
CC
= max,
TTL input levels
Outputs unloaded,
f
CLK
= max
V
CC
= max,
CMOS input levels
Outputs unloaded,
f
CLK
= max
Characteristic
*
Clock period
Clock High Time
Clock Low Time
A15:0, B15:0 setup to clock rising edge
A15:0, B15:0 hold after clock rising edge
MS, S2:0, ASI setup to clock rising edge
DEL, ASR,
CLR
setup to clock rising edge
DEL, ASR,
CLR
, MS, S2:0, ASI hold after
clock rising edge
CEA
,
CEB
setup to clock falling edge
CEA
,
CEB
hold after clock falling edge
Clock rising edge to OVR, C15:0, D15:0
OEC
/
OED
low to C15:0/D15:0 high data valid
OEC
/
OED
low to C15:0/D15:0 low data valid
OEC
/
OED
high to C15:0/D15:0 high impedance
Vcc current
Vcc current
SWITCHING CHARACTERISTICS
Max.
-
-
-
-
-
-
-
-
-
-
40
40
40
40
70
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
PDSP16318
Min.
100
20
20
8
2
10
8
2
2
8
5
-
-
-
-
-
Value
Military
Sub
group
9, 10, 11
All parameters marked * are tested during production.
All parameters marked are guaranteed by design and characterisation.
NOTES
1.
2.
3.
LSTTL is equivalent to I
= 20 microamps, I
OL
= -0.4mA
Current is defined as negative into the device
CMOS input levels are defined as:
V
IL
= 0.5V
V
IH
= V
DD
- 0.5V
Sub
group
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
相關PDF資料 |
PDF描述 |
|---|---|
| PDSP16318GC1R | CAT5E PATCH CORD SNAGLESS, GREEN 100FT |
| PDSP16318MC | PDSP16256GC1R |
| PDSP16318A | PDSP16256GC1R |
| PDSP16318 | Complex Accumulator(復雜累加器（由兩個獨立的20位加法器/減法器組成）) |
| PDSP16318A | Complex Accumulator(復雜累加器（由兩個獨立的20位加法器/減法器組成）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16330 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Pythagoras Processor |
| PDSP16330A | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Pythagoras Processor |
| PDSP16330A/IG/GC1R | 制造商:Microsemi Corporation 功能描述:PYTHAGORAS PROCESSOR 100PQFP - Tape and Reel |
| PDSP16330A0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
| PDSP16330A0GG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Other/Special/Miscellaneous Converter |
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