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參數資料
| 型號： | PDM4M3120S12M |
| 廠商： | IXYS CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 32 MULTI DEVICE SRAM MODULE, 12 ns, SMA72 |
| 封裝： | SIMM-72 |
| 文件頁數： | 8/10頁 |
| 文件大?。?/td> | 108K |
| 代理商： | PDM4M3120S12M |
PDM4M3120
8
Rev 1.1
PRELIMINARY
Timing Waveforms of Write Cycle No.1 (
WE
Controlled)
(1,2,3,7)
Timing Waveforms of Write Cycle No.2 (
CS
Controlled)
(1,2,3,5)
NOTES 1
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
or
WE
going HIGH to end the write cycle.
4. During this period, I/O pins are in the output state, and input signals must be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs
remain in a high-impedance state.
6. Transition is measured
±
200 mV for steady state with a 5 pF load (including scope and jig). This
parameter is determined by device characteristics but is not production tested.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or
(t
WHZ
+ t
) to allow the I/O drivers to turn off and data to be placed on the bus for the required t
DW
.
If
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write
pulse width can be as short as the specified t
WP
.
t
AW
CS
t
AS
t
WR
t
WC
t
CW
t
DH
t
DW
D
IN
WE
ADDRESS
Data Valid
t
AW
CS
D
OUT
t
AS
t
WR
t
WC
t
WP(7)
t
WHZ(6)
t
OHZ(6)
t
OW(6)
t
OHZ (6)
t
DH
t
DW
D
IN
WE
OE
ADDRESS
Data Valid
(4)
(4)
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