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參數資料
| 型號： | PDM41028SA15TSOTY |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1 Megabit Static RAM 256K x 4-Bit |
| 中文描述： | 1兆位靜態(tài)RAM 256K × 4位 |
| 文件頁數： | 7/8頁 |
| 文件大?。?/td> | 133K |
| 代理商： | PDM41028SA15TSOTY |
PDM41028
Rev. 2.2 - 4/29/98
7
1
2
3
4
5
6
7
8
9
10
11
12
AC Electrical Characteristics
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table
Low V
CC
Data Retention Waveform
Data Retention Electrical Characteristics (LA Version Only)
NOTES: (For three previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured
±
200 mV from steady state voltage.
2. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. Chip Enable is held in its active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
7. Vcc = 5V
±
5%.
Description
-10
(7)
-12
(7)
-15
WRITE Cycle
Sym
Min.
Max.
Min.
Max.
Min.
Max.
Units
WRITE Cycle time
t
WC
10
12
15
ns
Chip enable active time
t
CW
10
10
11
ns
Address Valid to end of write
t
AW
10
10
11
ns
Address setup time
t
AS
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
ns
Write pulse width
t
WP1
9
10
11
ns
Write pulse width
t
WP2
10
11
12
ns
Data setup time
t
DS
7
7
7
ns
Data hold time
t
DH
0
0
0
ns
Write disable to output in low Z
(1,3)
t
LZWE
0
0
0
ns
Write enable to output in high Z
(1,3)
t
HZWE
7
7
7
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DR
VCC for Retention Data
2
—
—
V
I
CCDR
Data Retention Current
CE
≥
V
CC
– 0.2V
V
IN
≥
V
CC
– 0.2V
or
≤
0.2V
V
CC
= 2V
—
—
500
μ
A
V
CC
= 3V
—
—
750
μ
A
t
CDR
t
R(3)
Chip Deselect to Data Retention Time
0
—
—
ns
Operation Recovery Time
t
RC
—
—
ns
DON'T CARE
VCC
V
V
IH
IL
t
CDR
V
t
R
4.5V
4.5V
Data Retention Mode
CE
DR
VDR
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