參數(shù)資料
型號(hào): PDM21096LL12ST
元件分類: SRAM
英文描述: 512K X 8 STANDARD SRAM, 120 ns, PDSO32
封裝: PLASTIC, STSOP1-32
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 277K
代理商: PDM21096LL12ST
Rev. 0.0 - 4/30/98
1
ADVANCED
Features
n High-speed access times
Com’l: 100 and 120 ns
n Low power operation (typical)
- PDM21096LL
Active: 65 mW
Standby: 7
W
n Single +2.7V (±0.3V) power supply
n TTL-compatible inputs and outputs
n I/Os are 3.6V tolerant
n Low data retention voltage: 1.5V
n Packages
Plastic TSOP (I) - T
Plastic STSOP (I) - ST
Description
The PDM21096LL is a very low power CMOS static
RAM organized as 524,288 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
The PDM21096LL operates from a single +2.7V
power supply and all the inputs and outputs are
fully TTL- compatible. The device supports low data
retention voltage for battery back-up operation with
low current.
The PDM21096LL is available in a 32-pin plastic
TSOP (I) and a 32-pin plastic STSOP (I).
A
A
0
18
I/O
I/O
0
7
CE
WE
Addresses
Decoder
Memory
Matrix
Input
Data
Control
Column I/O
OE
Control
Functional Block Diagram
PDM21096LL
512K x 8-Bit Low Power
2.7 Volt
相關(guān)PDF資料
PDF描述
PDM31096LL100ST 512K X 8 STANDARD SRAM, 100 ns, PDSO32
PDM31516SA15TTR 64K X 8 STANDARD SRAM, 15 ns, PDSO44
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PDM31548SA12SOATY 128K X 16 STANDARD SRAM, 12 ns, PDSO44
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