參數(shù)資料
型號(hào)： PDI1394P22
廠商： NXP Semiconductors N.V.
英文描述： 3-port Physical Layer Interface(三端口物理層接口)
中文描述： 三端口物理層接口（三端口物理層接口）
文件頁(yè)數(shù)： 5/30頁(yè)
文件大小： 163K
代理商： PDI1394P22
Philips Semiconductors
Objective specification
PDI1394P22
3-port physical layer interface
1999 Jul 09
5
Name
Description
I/O
Pin Numbers
Pin Type
R0, R1
Bias
54, 55
—
Current setting resistor terminals. These terminals are connected to
an external resistance to set the internal operating currents and
cable driver output currents. A resistance of 6.34 k
±
1% is required to
meet the IEEE Std 1394–1995 output voltage limits.
SYSCLK
CMOS
63
O
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
TEST0
CMOS
29
I
Test control input. This input is used in manufacturing tests of the
PDI1394P22. For normal use, this terminal should be tied to GND.
TEST1
CMOS
28
I
Test control input. This input is used in manufacturing tests of the
PDI1394P22. For normal use, this terminal should be tied to GND.
TPA0+,
TPA1+,
TPA2+
Cable
36, 41, 47
I/O
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential sig
matched and as short as possible to the external load resistors and to
the cable connector.
TPA0–,
TPA1–,
TPA2–
Cable
35, 40, 46
I/O
TPB0+,
TPB1+,
TPB2+
Cable
34, 39, 45
I/O
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential sig
matched and as short as possible to the external load resistors and to
the cable connector.
TPB0–,
TPB1–,
TPB2–
Cable
33, 38, 44
I/O
TPBIAS0,
TPBIAS1,
TPBIAS2
Cable
37, 42, 48
I/O
Twisted-pair bias output. This provides the 1.86V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. Each of these terminals must be decoupled with a
0.3
μ
F–1
μ
F capacitor to ground.
XO, XI
Crystal
60, 59
—
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case).
相關(guān)PDF資料
PDF描述
PDI1394P24 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口)
PDI40C1D00
PDI40C1300
PDI40C130R
PDI40C130X
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394P22BD 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:3-port physical layer interface
PDI1394P23 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:2-port/1-port 400 Mbps physical layer interface
PDI1394P23BD 功能描述:IC IEEE 1394 LINK CTRLR 64LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2
PDI1394P23BD,118 功能描述:輸入/輸出控制器接口集成電路 1394 2-PORT PHY NO NEW DESIGNS RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
PDI1394P23BD,151 功能描述:輸入/輸出控制器接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*