
μ
PD784054(A)
5
CONTENTS
1.
DIFFERENCES BETWEEN
μ
PD784054(A) AND
μ
PD784044(A), 784046(A) .................................7
2.
PIN CONFIGURATION (Top View) .....................................................................................................8
3.
SYSTEM CONFIGURATION EXAMPLE...........................................................................................10
4.
BLOCK DIAGRAM .............................................................................................................................11
5.
PIN FUNCTIONS ................................................................................................................................12
5.1
Port Pins .................................................................................................................................................... 12
5.2
Pins Other Than Port Pins ...................................................................................................................... 14
5.3
I/O Circuits of Pins and Processing of Unused Pins .......................................................................... 16
6.
CPU ARCHITECTURE .......................................................................................................................18
6.1
Memory Space .......................................................................................................................................... 18
6.2
CPU Registers........................................................................................................................................... 20
6.2.1
General-purpose registers ............................................................................................................. 20
6.2.2
Control registers ............................................................................................................................. 21
6.2.3
Special function registers (SFRs).................................................................................................. 22
7.
PERIPHERAL HARDWARE FUNCTIONS........................................................................................27
7.1
Ports ........................................................................................................................................................... 27
7.2
Clock Generation Circuit......................................................................................................................... 28
7.3
Timer .......................................................................................................................................................... 30
7.4
A/D Converter ........................................................................................................................................... 32
7.5
Serial Interface.......................................................................................................................................... 33
7.5.1
Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................................... 34
7.6
Edge Detection Circuit ............................................................................................................................ 36
7.7
Watchdog Timer........................................................................................................................................ 36
8.
INTERRUPT FUNCTION....................................................................................................................37
8.1
Interrupt Source ....................................................................................................................................... 37
8.2
Vectored Interrupt .................................................................................................................................... 39
8.3
Context Switching .................................................................................................................................... 40
8.4
Macro Service ........................................................................................................................................... 41
9.
LOCAL BUS INTERFACE .................................................................................................................44
9.1
Memory Expansion .................................................................................................................................. 45
9.2
Memory Space .......................................................................................................................................... 46
9.3
Programmable Wait.................................................................................................................................. 46
9.4
Bus Sizing Function................................................................................................................................. 46