
CHAPTER 23 LOW-VOLTAGE DETECTOR
User’s Manual U16228EJ2V0UD
415
(2) Low-voltage detection level selection register (LVIS)
This register selects the low-voltage detection level.
This register can be set by an 8-bit memory manipulation instruction.
RESET input clears LVIS to 00H.
Figure 23-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
Address: FFBFH After reset: 00H R/W
0
LVIS0
1
LVIS1
2
LVIS2
3
0
4
0
5
0
6
0
7
0
Symbol
LVIS
LVIS2
LVIS1
LVIS0
Detection level
0
0
0
V
LVI0
(4.3 V
±
0.2 V)
0
0
1
V
LVI1
(4.1 V
±
0.2 V)
0
1
0
V
LVI2
(3.9 V
±
0.2 V)
0
1
1
V
LVI3
(3.7 V
±
0.2 V)
1
0
0
V
LVI4
(3.5 V
±
0.2 V)
Note 1
1
0
1
V
LVI5
(3.3 V
±
0.15 V)
Notes 1, 2
1
1
0
V
LVI6
(3.1 V
±
0.15 V)
Notes 1, 2
1
1
1
Setting prohibited
Notes 1.
When the detection voltage of the POC circuit is specified as V
POC
= 3.5 V
±
0.2 V by a mask
option, do not select V
LVI4
to V
LVI6
as the LVI detection voltage. Even if V
LVI4
to V
LVI6
are
selected, the POC circuit has priority.
2.
This setting is prohibited in (A1) grade products and (A2) grade products.
Caution Be sure to clear bits 3 to 7 to 0.