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參數(shù)資料
| 型號： | PCM69AU |
| 英文描述： | Advanced 1-Bit BiCMOS Dual 18-Bit DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 先進的1位的BiCMOS雙18位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 95K |
| 代理商： | PCM69AU |
8
PCM67/69A
INSTALLATION
POWER SUPPLIES
Refer to “Pin Configuration” diagram for proper connection
of the PCM67/69A. The PCM67/69A requires only a +5V
supply. Both analog and digital supplies should be tied to-
gether at a single point, as no real advantage is gained by using
separate supplies. It is more important that both these supplies
be as “clean” as possible to reduce coupling of supply noise to
the output.
FILTER CAPACITOR REQUIREMENTS
As shown in the “Pin Configuration” diagram, various sizes of
decoupling capacitors can be used with no special tolerances
required. All capacitors should be as close to the appropriate
pins of the PCM67/69A as possible to reduce noise pickup
from surrounding circuitry.
A power supply decoupling capacitor should be used near the
analog supply pin to maximize power supply rejection, as
shown in Figure 6, regardless of how good the supplies are.
Both commons should be connected to an analog ground
plane as close to the PCM67/69A as possible.
The value of these capacitors is influenced by actual board
layout design and noise from power supplies and other digital
input lines.
The best suitable value for the capacitors should be deter-
mined by the user’s actual application board.
FIGURE 6. Shift of I/V Out Voltage.
SHIFT OF I/V OUT VOLTAGE
If the user requires a bipolar voltage output centered around
0V or one-half of V
CC
, the output can be shifted by adding an
offset current on the inverting point of the I/V op amp as
shown in Figure 6.
FIGURE 7. Useful Application Circuit for Shift of I/V Out
Voltage.
INTERFACE CONTROL FUNCTION
Both the PCM67 and PCM69A (SOIC package type) are
capable of 16-bit L/R serial input and 20-bit L/R parallel input
as shown in Table 3.
R
OS
R
NF
+V
CC
I
OUT
V
(3.5V)
V
CC
2
or 0V
V
S
V
O
V
OUT
In case of shift to
±
3V swing, 0V center
OUT
R
NF
= 1.2mA
1.2mA
6V
–FSR±(V
) = –3V after offset addition, shift voltage
V
SHT
is given by
V
SHT
= V
COM
+ 3V = 3.5 + 3 = 6.5V
Offset Current I
OS
is given by
SHT
I
OS
= V
R
NF
5k
6.5V
Offset Resistor R
OS
is given by
CC
– V
COM
R
OS
= V
I
OS
1.3mA
5 – 3.5V
V
O
2
V
(+3.5V)
V
O
V
COM
+
V
SHT
I
OS
MC1
MC2
MC3
DATA-R
INPUT FORMAT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
X
X
X
X
16-Bit L/R Serial
(1)
16-Bit L/R Serial
(1)
18-Bit L/R Serial
(1)
18-Bit L/R Serial
(1)
20-Bit L/R Parallel
20-Bit L/R Parallel
18-Bit L/R Parallel
18-Bit L/R Parallel
[WDCK Invert]
[WDCK Invert]
L R
L R
R
R
L
L
WDCK
WDCK
L R
L R
R
R
L
L
WDCK
WDCK
NOTE: (1) Data input to Data-Lch (Pin 17) for L/R serial format.
TABLE III. Interface Control Function of SOIC.
MC1
DATA-R
INPUT FORMAT
0
0
1
0
1
X
18-Bit L/R Serial
18-Bit L/R Serial
18-Bit L/R Parallel
TABLE IV. Interface Control Function of DIP.
L R
L R
R
R
L
L
WDCK
WDCK
PCM67P and PCM69AP (DIP package) have only 18-bit
L/R serial input function as shown in Table 4.
R
2
330
R
NF
5k
+V
(+5V)
I
OUT
V
COM
0V
6V
V
OUT
R
1
820
+
+
C
1
C
2
10
μ
F ~ 100
μ
F
10
μ
F ~ 100
μ
F
Note: R
1
and C
are noise de-coupling circuits from noise
on +V
CC
power supply line.
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