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參數資料
| 型號： | PCM63 |
| 英文描述： | Colinear⑩ 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 共線⑩20位單片音頻數字模擬轉換器 |
| 文件頁數： | 7/10頁 |
| 文件大?。?/td> | 254K |
| 代理商： | PCM63 |
7
PCM63P
Offset, Gain, And Temperature Drift
Although the PCM63P is primarily meant for use in dy-
namic applications, specifications are also given for more
traditional DC parameters such as gain error, bipolar zero
offset error, and temperature gain and offset drift.
DIGITAL INPUT
Timing Considerations
The PCM63P accepts TTL compatible logic input levels.
Noise immunity is enhanced by the use of differential
current mode logic input architectures on all input signal
lines. The data format of the PCM63P is binary two’s
complement (BTC) with the most significant bit (MSB)
being first in the serial input bit stream. Table II describes
the exact relationship of input data to voltage output coding.
Any number of bits can precede the 20 bits to be loaded,
since only the last 20 will be transferred to the parallel DAC
register after LE (P20, Latch Enable) has gone low.
All DAC serial input data (P21, DATA) bit transfers are
triggered on positive clock (P18, CLK) edges. The serial-to-
parallel data transfer to the DAC occurs on the falling edge
of Latch Enable (P20, LE). The change in the output of the
DAC coincides with the falling edge of Latch Enable (P20,
LE). Refer to Figure 2 for graphical relationships of these
signals.
Maximum Clock Rate
A typical clock rate of 16.9MHz for the PCM63P is derived
by multiplying the standard audio sample rate of 44.1kHz by
sixteen times (16
x
oversampling) the standard audio word
bit length of 24 bits (44.1kHz
x
16
x
24 = 16.9MHz). Note
that this clock rate accommodates a 24-bit word length, even
though only 20 bits are actually being used. The maximum
clock rate of 25MHz is guaranteed, but is not 100% final
tested. The setup and hold timing relationships are shown in
Figure 3.
“Stopped Clock” Operation
The PCM63P is normally operated with a continuous clock
input signal. If the clock is to be stopped between input data
words, the last 20 bits shifted in are not actually shifted from
the serial register to the latched parallel DAC register until
Latch Enable (LE, P20) goes low. Latch Enable must remain
low until after the first clock cycle of the next data word
to insure proper DAC operation. In any case, the setup and
hold times for Data and LE must be observed as shown in
Figure 3.
FIGURE 2. Timing Diagram.
NOTES: (1) If clock is stopped between input of 20-bit data words, Latch Enable (LE) must remain low until after the first clock cycle of the next 20-bit data
word stream. (2) Data format is binary two’s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable
(LE) must remain low at least one clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle before going negative.
(5) I
OUT
changes on negative going edge of Latch Enable (LE).
P18 (Clock)
P21 (Data)
P20 (Latch Enable)
P6 (I )
1
2
3
12
13
14
15
16
17
18
19
20
4
1
MSB
LSB
VOLTAGE OUTPUT
(With External Op Amp)
DIGITAL INPUT
ANALOG OUTPUT
CURRENT OUTPUT
1,048,576LSBs
1LSB
7FFFF
HEX
00000
HEX
FFFFF
HEX
80000
HEX
Full Scale Range
NA
+Full Scale
Bipolar Zero
Bipolar Zero – 1LSB
–Full Scale
4.00000000mA
3.81469727nA
–1.99999619mA
0.00000000mA
+0.00000381mA
+2.00000000mA
6.00000000V
5.72204590
μ
V
+2.99999428V
0.00000000V
–0.00000572V
–3.00000000V
TABLE II. Digital Input/Output Relationships.
FIGURE 3. Setup and Hold Timing Diagram.
Data
Input
Clock
Input
Latch
Enable
LSB
MSB
>One Clock Cycle
>20ns
>10ns
>15ns
>15ns
>1ns
>33ns
>10ns
>One Clock Cycle
>10ns
相關PDF資料 |
PDF描述 |
|---|---|
| PCM63P | Colinear⑩ 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM63P-J | Colinear⑩ 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM63P-K | Colinear⑩ 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM64D | 18-Bit Digital-to-Analog Converter |
| PCM67 | Advanced 1-Bit BiCMOS Dual 18-Bit DIGITAL-TO-ANALOG CONVERTER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCM-63 | 功能描述:電線鑒定 Pre-Printed WM Card, Vinyl Cloth, .22" W RoHS:否 制造商:TE Connectivity / Q-Cees 產品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
| PCM6-300-000 | 制造商:PACTEC 功能描述:TOP&BOTTOM+HARDWARE ONLY |
| PCM-6308V+ | 功能描述:數據記錄與采集 ISOLATED 8CH 12BIT VOLTAGE OUTPUT CARD RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
| PCM63P | 制造商:BB 制造商全稱:BB 功能描述:Colinear⑩ 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM63P-J | 制造商:BB 制造商全稱:BB 功能描述:Colinear⑩ 20-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
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