參數(shù)資料
型號: PCM4204PAPT
元件分類: ADC
英文描述: HIGH PERFORMANCE 24 BIT 216KHZ SAMPLING FOUR CHANNEL AUDIO ANALOG TO DIGITAL CONVERTER
中文描述: 高性能的24位216kHz的最大采樣四通道音頻模數(shù)轉(zhuǎn)換器
文件頁數(shù): 17/34頁
文件大?。?/td> 554K
代理商: PCM4204PAPT
$%
SBAS327A JUNE 2004 REVISED SEPTEMBER 2004
www.ti.com
17
Table 4. Sampling Mode Selection for DSD
Output Mode Operation
FS2
FS1
FS0
SAMPLING MODE
0
0
0
128fS DSD Output Rate with fSCKI = 768fS
128fS DSD Output Rate with fSCKI = 512fS
128fS DSD Output Rate with fSCKI = 384fS
128fS DSD Output Rate with fSCKI = 256fS
64fS DSD Output Rate with fSCKI = 384fS
64fS DSD Output Rate with fSCKI = 256fS
Reserved
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Reserved
Table 5. Sampling Mode Selection for DSD Input
Mode Operation
FS2
0
FS1
0
FS0
0
SAMPLING MODE
Reserved
0
0
1
128fS DSD Output Rate with fSCKI = 512fS
128fS DSD Output Rate with fSCKI = 384fS
128fS DSD Output Rate with fSCKI = 256fS
64fS DSD Output Rate with fSCKI = 384fS
64fS DSD Output Rate with fSCKI = 256fS
Reserved
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Reserved
AUDIO DATA FORMATS
As mentioned previously, the PCM4204 supports 24-bit
linear PCM output data, as well as 1-bit DSD output data.
The available data formats are dependent upon whether
the PCM4204 is configured in Slave or Master mode. The
S/M (pin 17), FMT0 (pin 18), FMT1 (pin 19), and FMT2 (pin
20) inputs are utilized to select either Slave or Master
mode and the corresponding audio data format.
In Slave mode, the PCM bit and left/right word clocks (BCK
and LRCK) are configured as input pins. DSD data formats
are not supported in Slave mode. Slave mode supports
commonly used PCM audio data formats, including Left-
Justified, Right-Justified, and Philips I
2
S. Time division
multiplexed (TDM) data formats are also supported,
allowing up to two PCM4204 devices to be cascaded on
a single audio serial bus. Table 6 summarizes the
corresponding Slave mode data format selections.
In Master mode, the PCM bit and left/right clocks (BCK and
LRCK respectively) are configured as output pins, and are
derived from the system clock input (SCKI). For the DSD
data and clock pins (DSD1, DSD2, DSD3, DSD4, and
DSDCLK), they may be configured as either inputs or
outputs, depending upon the DSD format selection. Table
7 summarizes the corresponding Master mode data format
selections.
Figure 3, Figure 4, and Figure 5 illustrate the PCM and
DSD data formats supported by the PCM4204.
Table 6. Slave Mode Audio Data Format Selection
S/M
FMT2
FMT1
FMT0
AUDIO DATA FORMAT
1
0
0
0
24-bit Left-Justified
24-bit I2S
1
0
0
1
1
0
1
0
24-bit Right-Justified
1
0
1
1
TDM with No BCK Delay for
Start of Frame
1
1
0
0
TDM with One BCK Delay for
Start of Frame
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
Table 7. Master Mode Audio Data Format
Selection
S/M
FMT2
FMT1
FMT0
AUDIO DATA FORMAT
0
0
0
0
24-bit Left-Justified
24-bit I2S
0
0
0
1
0
0
1
0
24-bit Right-Justified
0
0
1
1
DSD Output with PCM Output
Disabled
0
1
0
0
DSD Input with 24Bit Right-
Justified PCM Output
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
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