參數(shù)資料
型號: PCM3794RHBR
元件分類: Codec
英文描述: 16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital Speaker Amplifier
中文描述: 16位,低功耗立體聲音頻編解碼器麥克風(fēng)偏置,耳機(jī),揚(yáng)聲器放大器和數(shù)字
文件頁數(shù): 26/63頁
文件大?。?/td> 915K
代理商: PCM3794RHBR
www.ti.com
Three-Wire Interface (SPI) Timing Requirements
t
w(MCH)
50% of V
IO
MS
t
(MLS)
LSB
50% of V
IO
50% of V
IO
t
w(MCL)
t
w(MHH)
t
(MLH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
T0013-08
TWO-WIRE INTERFACE [I
2
C, MODE (PIN 28) = HIGH]
The PCM3793/94 supports the I
2
C serial bus and the data transmission protocol for the I
2
C standard as a slave
device. This protocol is explained in I
2
C specification 2.0.
In I
2
C mode, the control terminals are changed as follows.
SLAVE ADDRESS
MSB
PCM3793
PCM3794
SLES193A–AUGUST 2006–REVISED SEPTEMBER 2006
Figure 31
shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
PARAMETERS
MIN
500
(1)
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
t
(MCY)
t
w(MCL)
t
w(MCH)
t
w(MHH)
t
(MLS)
t
(MLH)
t
(MDH)
t
(MDS)
MC pulse cycle time
MC low level time
MC high level time
MS high level time
MS falling edge to MC rising edge
MS hold time
MD hold time
MD setup time
50
50
(1)
20
20
15
20
(1)
3/(128 f
S
) s (min), where f
S
is sampling rate.
Figure 31. SPI Interface Timing
TERMINAL NAME
MS/ADR
MD/SDA
MC/SCL
PROPERTY
Input
Input/output
Input
DESCRIPTION
I
2
C address
I
2
C data
I
2
C clock
LSB
1
0
0
0
1
1
ADR
R/W
The PCM3793/94 has its own 7-bit slave address. The first six bits (MSBs) of the slave address are factory
preset to 100011. The last bit of the address byte is the device select bit, which can be user-defined by the ADR
terminal. A maximum of two PCM3793/94s can be connected on the same bus at one time. Each PCM3793/94
responds when it receives its own slave address.
26
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相關(guān)PDF資料
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