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參數(shù)資料
| 型號： | PCM3501 |
| 元件分類： | Codec |
| 英文描述： | Low Voltage, Low Power, 16-Bit, Mono VOICE/MODEM CODEC |
| 中文描述： | 低電壓，低功耗，16位，單聲道語音/調(diào)制解調(diào)器編解碼器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 182K |
| 代理商： | PCM3501 |
18
PCM3501
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
BCKP
t
BCKH
t
BCKL
t
FSW
t
FSP
t
FSSU
t
FSHD
t
DISU
t
DIHD
t
CKDO
t
HZDO
t
DOHZ
t
FSOW
t
BFSO
t
R
t
F
BCK Period
BCK Pulse Width HIGH
BCK Pulse Width LOW
FS Pulse Width HIGH
FS Period
FS Set Up TIme to BCK Rising Edge
FS Hold TIme to BCK RIsing Edge
DIN Set Up Time to BCK Rising Edge
DIN Hold Time to BCK Rising Edge
Delay Time BCK Falling Edge to DOUT
Delay Time BCK Falling Edge to DOUT Active
Delay Time BCK Falling Edge to DOUT Inactive
FSO Pulse Width HIGH
Delay Time BCK Falling Edge to FSO
Rising Time of All Signals
Falling Time of All Signals
600
200
200
ns
ns
ns
ns
t
BCKP
– 60
t
BCKP
1/f
S
t
BCKP
+ 60
60
60
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
20
19.5
t
BCKP
t
BCKP
– 60
0
t
BCKP
+ 60
80
30
30
FIGURE 13. Serial Interface Timing for Time Slot Mode Operation (Slave Mode).
Table III shows the TSC pin settings and corresponding
mode selections. When Time Slot Mode is enabled, FSO
(pin 12) is used as a frame sync output, which is connected
to the FS input of the next PCM3501 in the Time Slot
sequence. Figures 13 and 14 provide detailed timing for
Time Slot Mode operation.
TSC (PIN 7)
TIME SLOT MODE
0
1
Time Slot Mode Disabled, Normal Operation
Time Slot Operation Enable
LOOP (PIN 19)
LOOP-BACK MODE
0
1
Loop-Back Mode Disabled, Normal Operation
Loop-Back Mode Enabled
TABLE IV. Loop-Back Mode Selection.
TABLE III. Time Slot Mode Selection.
HPFD (PIN 18)
HIGH-PASS FILTER MODE
0
1
High-Pass Filter On
High-Pass Filter Off
TABLE V. High-Pass Filter Mode Selection.
HIGH-PASS FILTER
The PCM3501 includes a digital high-pass filter in the ADC
which may be used to remove the DC offset created by the
analog front-end (AFE) section. The high-pass filter response
is shown in Figure 15. The high-pass filter may be enabled or
disabled using the HPFD input (pin 18). Table V shows the
HPFD pin settings and corresponding mode selections.
ADC-TO-DAC LOOP BACK
The PCM3501 includes a Loop-Back Mode, which directly
feeds the ADC data to the DAC input. This mode is
designedfor diagnostic testing and system adjustment. Loop-
Back Mode is enabled and disabled using the LOOP input
(pin 19). Table IV shows the LOOP pin settings and corre-
sponding mode selections. The serial interface continues to
operate in Loop-Back Mode, allowing the host to read the
ADC data at the DOUT pin.
t
FSW
t
FSSU
High Impedance
High Impedance
0.5V
DD
t
FSHD
t
BCKP
t
BCKL
t
DISU
t
DIHD
t
BCKH
t
CKDO
t
HZDO
t
DOHZ
t
FSP
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, and FSO signal is 50pF.
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
t
FSOW
t
BFSO
FS
(input)
BCK
(input)
DIN
(input)
DOUT
(output)
FSO
(output)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PCM3501E | 功能描述:接口—CODEC Lo-Vlt Lo-Pwr Mono Voice/Modem Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3501E/2K | 功能描述:接口—CODEC Lo-Vlt Lo-Pwr Mono Voice/Modem Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3501E/2KG4 | 功能描述:接口—CODEC Lo-Vlt Lo-Pwr Mono Voice/Modem Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3501EG4 | 功能描述:接口—CODEC Lo-Vlt Lo-Pwr Mono Voice/Modem Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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