參數(shù)資料
型號(hào): PCM3052ARTFR
元件分類: Codec
英文描述: 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA
中文描述: 24位,96千赫立體聲音頻編解碼器麥克風(fēng)放大器,偏見,MUXTIPLEXER,和PGA
文件頁(yè)數(shù): 20/45頁(yè)
文件大小: 583K
代理商: PCM3052ARTFR
www.ti.com
THEORY OF OPERATION
ADC SECTION
The ADC block consists of a reference circuit, two channels of single-ended to differential converter, a fifth-order
delta-sigma modulator with fully differential architecture, a decimation filter with high-pass filter, and a serial
interface circuit which is also used as the serial interface for the DAC input signal as shown in the block diagram.
1
st
SW-CAP
Integrator
Analog
In
X(z)
+
+
2
nd
SW-CAP
Integrator
3
rd
SW-CAP
Integrator
+
4
th
SW-CAP
Integrator
+
+
+
+
+
+
+
+
5
th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
B0005-02
DAC SECTION
The DAC section is based on the delta-sigma modulator, which consists of an 8-level amplitude quantizer and a
fourth-order noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A
block diagram of the 8-level delta-sigma modulator is shown in
Figure 40
. This 8-level delta-sigma modulator has
the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined
oversampling rate of the delta-sigma modulator and the internal 8
×
interpolation filter is 64 f
S
for all system
clocks. The theoretical quantization-noise performance of the 8-level delta-sigma modulator is shown in
Figure 41
.
PCM3052A
SLES160–NOVEMBER 2005
Figure 39
is the block diagram of the fifth-order delta-sigma modulator and transfer function.
An on-chip reference circuit with two external capacitors provides all reference voltages that are needed in the
ADC section, and defines the full-scale voltage range of both channels.
An on-chip, single-ended to differential signal converter saves the design, space, and extra parts cost of an
external signal converter.
Full differential architecture provides a wide dynamic range and excellent power supply rejection performance.
The input signal is sampled at
×
64 oversampling rate and an on-chip antialiasing filter eliminates the need for an
external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using the
switched-capacitor technique and a comparator, shapes the quantization noise generated outside of audio signal
band by the comparator and 1-bit DAC.
The high-order delta-sigma modulation randomizes the modulator outputs and reduces idle-tone level.
The 64 f
, 1-bit stream from the delta-sigma modulator is converted to a 1-f
S
, 24-bit digital signal by removing
high-frequency noise components with the decimation filter.
The dc component of the signal is removed by the HPF, and the HPF output is converted to a time-multiplexed
serial signal through the serial interface.
Figure 39. Block Diagram of Fifth-Order Delta-Sigma Modulator
20
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCM3052ARTFRG4 功能描述:接口—CODEC 24B Stereo Audo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
PCM3052RTFR 制造商:Texas Instruments 功能描述:
PCM3060 制造商:BB 制造商全稱:BB 功能描述:24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC
PCM3060PW 功能描述:接口—CODEC 24B 96/192kHz Asynchronous Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
PCM3060PW 制造商:Texas Instruments 功能描述:LEADED PROCESS COMPATIBLE:YES