- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367828 > PCM3052A 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA PDF資料下載
參數(shù)資料
| 型號： | PCM3052A |
| 元件分類： | Codec |
| 英文描述： | 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA |
| 中文描述： | 24位，96千赫立體聲音頻編解碼器麥克風放大器，偏見，MUXTIPLEXER，和PGA |
| 文件頁數(shù)： | 22/45頁 |
| 文件大?。?/td> | 583K |
| 代理商： | PCM3052A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
www.ti.com
SYSTEM CLOCK
The system clock for the PCM3052A must be 256 f
S
, where f
S
is the audio sampling rate, 16 kHz to 96 kHz.
Table 1
lists typical system clock frequencies, and
Figure 43
illustrates the system clock timing.
t
w(SCKH)
t
w(SCKL)
2 V
0.8 V
1/256 f
S
T000510
System Clock
POWER SUPPLY ON, EXTERNAL RESET, AND POWER DOWN
The PCM3052A has both an internal power-on-reset circuit and an external reset circuit. The sequences for both
resets are shown as follows.
PCM3052A
SLES160–NOVEMBER 2005
THEORY OF OPERATION (continued)
Table 1. Typical System Clock
SAMPLING RATE
FREQUENCY (f
S
) – LRCK
SYSTEM CLOCK FREQUENCY – MHz
256 f
S
4.096
8.192
11.2896
12.288
24.576
16 kHz
32 kHz
44.1 kHz
48 kHz
96 kHz
PARAMETER
MIN
16
16
MAX
UNIT
ns
ns
t
w(SCKH)
t
w(SCKL)
System clock pulse duration, HIGH
System clock pulse duration, LOW
Figure 43. System Clock Timing
Figure 44
is the timing chart of the internal power-on reset. Two power-on-reset circuits are implemented, one
each for for V
1 and V
. Initialization (reset) is performed automatically at the time when V
CC
1 and V
DD
exceed
3.9 V (typical) and 2.2 V (typical), respectively.
Internal reset is released after 1024 SCKI from power-on-reset release, and the PCM3052A begins normal
operation. V
L and V
R from the DAC are forced to the V
COM
(= 0.5 V
CC
2) level as V
2 rises. When
synchronization between SCKI, BCK, and LRCK is maintained, V
OUT
L and V
OUT
R go into the fade-in sequence.
Then V
OUT
L and V
OUT
R provide outputs corresponding to DIN after t
(DACDLY1)
= 2100/f
S
from power-on-reset
release. On the other hand, DOUT from the ADC provides an output corresponding to V
L and V
R after
t
(ADCDLY1)
= 4500/f
S
from power-on-reset release. If synchronization is not maintained, the internal reset is not
released, and operation is kept in the power-down mode. After resynchronization, the DAC goes into the fade-in
sequence, and the ADC goes into normal operation after internal initialization.
DOUTS can provide S/PDIF data after the power-on-reset release if the SPDIF bit is HIGH (see serial control
port for mode control section).
Figure 45
shows timing chart for external reset. The PDWN pin (pin 9) initiates external forced reset when PDWN
= LOW, and it provides the power-down mode, which is the lowest power-dissipation state in the PCM3052A.
When PDWN transitions from HIGH to LOW while SCKI, BCK, and LRCK are synchronized, V
OUT
L and V
OUT
R
are faded out and forced into V
(= 0.5 V
2) level after t
= 2100/f
. At the same time as the internal
reset becomes LOW, DOUT becomes ZERO, the PCM3052A enters the power-down mode. To return to normal
operation, set PDWN to HIGH. Then the power-on reset sequence,
Figure 44
, is performed.
22
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCM3052ARTF | 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA |
| PCM3052ARTFG4 | 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA |
| PCM3052ARTFR | 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA |
| PCM3052ARTFRG4 | 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA |
| PCM3501 | Low Voltage, Low Power, 16-Bit, Mono VOICE/MODEM CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM3052ARTF | 功能描述:接口—CODEC 24B Stereo Audo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3052ARTFG4 | 功能描述:接口—CODEC 24B Stereo Audo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3052ARTFR | 功能描述:接口—CODEC 24B Stereo Audo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3052ARTFRG4 | 功能描述:接口—CODEC 24B Stereo Audo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3052RTFR | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。