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參數(shù)資料
| 型號(hào)： | PCM3002E |
| 元件分類： | Codec |
| 英文描述： | 16-/20-Bit Single-Ended Analog Input/Output STEREO AUDIO CODECs |
| 中文描述： | 16-/20-Bit單端模擬輸入/輸出立體聲編解碼器 |
| 文件頁(yè)數(shù)： | 20/23頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | PCM3002E |
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PCM3002/3003
20
LOP:
Bit 5
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I
2
S. In Format 3 (I
2
S Frame), Loop-
back is not supported.
ADC to DAC Loop-Back Control
LOP
0
1
Loop-back Disable (default)
Loop-back Enable
FMT (1,0)
Bit 3:2
Audio Data Format Select
These bits determine the input and output audio
data formats.
FMT1
FMT0
DAC
ADC
Data Format
Data Format
NAME
0
0
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Left-justified
Format 0 (default)
0
1
20-bit, MSB-first,
Right-justified
20-bit, MSB-first,
Left-justified
Format 1
1
0
20-bit, MSB-first,
Left-justified
20-bit, MSB-first,
Left-justified
Format 2
1
1
20-bit, MSB-first,
I
2
S
20-bit, MSB-first,
I
2
S
Format 3
LRP:
Bit 1
Polarity of LRCIN Applies only to
Formats 0 through 2.
LRP
0
1
Left-channel is “H”, Right-channel is “L”. (default)
Left-channel is “L”, Right-channel is “H”.
FIGURE 12. Typical Connection Diagram for PCM3002/3003.
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
+
4.7
μ
F
(2)
4.7
μ
F
(2)
+
+
+
+
1
μ
F
1
μ
F
Control
Interface
Audio
Interface
+3V Analog V
CC
Rch In
Lch In
SYSCLK
L/R CLK
BIT CLK
DATA OUT
DATA IN
0.1
μ
F
and
10
μ
F
(1)
0.1
μ
F and 10
μ
F
(1)
0.1
μ
F
and 10
μ
F
(1)
4.7
μ
F
(4)
+
4.7
μ
F
(4)
+
Rch Out
(5)
Lch Out
(5)
MC
(6)
/DEM0
(7)
MD
(6)
/DEM1
(7)
RST
(6)
/PDAD
(7)
ML
(6)
/PDDA
(7)
ZFLG
(6)
/20BIT
(7)
+
4.7
μ
F
(4)
+
10k
PCM3002/3003
V
CC
1
V
CC
1
V
IN
R
V
REF
L
V
REF
R
V
IN
L
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
BCKIN
DOUT
V
CC
2
AGND1
AGND2
V
COM
V
OUT
R
V
OUT
L
MC/DEM0
MD/DEM1
ZFLG/20BIT
DIN
V
DD
DGND
NOTES: (1) 0.1
μ
F ceramic and 10
μ
F tantalum, typical, depending on power supply quality and
pattern layout. (2) 4.7
μ
F typical, gives settling time with 30ms (4.7
μ
F x 6.4k
) time constant in
Power ON and Power-Down OFF period. (3) 1
μ
F typical, gives 5.3Hz cut-off frequency of input
HPF in normal operation and gives settling time with 30ms (1
μ
F x 30k
) time constant in Power
ON and Power -Down OFF period. (4) 4.7
μ
F typical, gives 3.4Hz cut-off frequency of output HPF
in normal operation and gives settling time with 47ms (4.7
μ
F x 10k
) time constant in Power ON
and Power-Down OFF period. (5) Post low pass filter with R
IN
>10k
, depending on requirement
of system performance. (6) MC, MD, ML, ZFLG, RST and 10k
pull-up resistor are for the
PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
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| PCM3002 | 16-/20-Bit Single-Ended Analog Input/Output SoundPlus8482， |
| PCM4104 | High-Performance, 24-Bit, 216kHz sampling, Four-channel Audio Digital-to-Analog Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM3002E | 制造商:Texas Instruments 功能描述:AUDIO CODEC IC 制造商:Texas Instruments 功能描述:IC, AUDIO CODEC, 20BIT, 48KHZ, SSOP-24 |
| PCM3002E/2K | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002E/2KG4 | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002EG | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002EG/2K | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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