參數(shù)資料
型號(hào)： PCM1851PJTR
英文描述： 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
中文描述： 24位，96千赫立體聲A / D轉(zhuǎn)換器6 × 2通道的MUX和PGA
文件頁(yè)數(shù)： 28/30頁(yè)
文件大?。?/td> 370K
代理商： PCM1851PJTR
PCM1850
PCM1851
SLES108
MARCH 2004
www.ti.com
28
BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
Pins
The digital and analog power supply lines to the PCM1850/1851 must be bypassed to the corresponding ground pins with
0.1-
μ
F ceramic and 10-
μ
F electrolytic capacitors as close to the pins as possible to maximize the dynamic performance
of the ADC.
AGND, DGND Pins
To maximize the dynamic performance of the PCM1850/1851, the analog and digital grounds are not connected internally.
These grounds must have low impedance to avoid digital noise feeding back into the analog ground. Therefore, they should
be connected directly to each other under the parts to reduce the potential of a noise problem.
V
IN
L[1:6], V
IN
R[1:6] Pins
A 0.33-
μ
F capacitor is recommended as the ac-coupling capacitor, which gives a 2.4- to 8.5-Hz cutoff frequency. If higher
full-scale input voltage is required, it can be adjusted by adding only one series resistor to each V
IN
xx pin, but a signal source
resistance less than 1 k
is recommended for these pins in order to keep accuracy of the gain control command and to
maintain crosstalk performance.
MOUTL, MOUTR Pins
An ac-coupled light load is recommended; a 2.2-
μ
F capacitor with a 10-k
load gives a 7.2-Hz cutoff frequency.
V
REF
1, V
REF
2, V
REF
S Pins
Between V
REF
1 and AGND, V
REF
2 and AGND, and V
REF
S and AGND, 0.1-
μ
F ceramic and 10-
μ
F electrolytic capacitors
are recommended to ensure low source impedance of the ADC references. These capacitors should be located as close
as possible to the V
REF
1, V
REF
2, and V
REF
S pins to reduce dynamic errors on the ADC references. The differential voltage
between V
REF
2 and AGND sets the analog input full-scale range.
BCK and LRCK Pins (in Master Mode), DOUT Pin
These pins have enough load driving capability. However, if the output line is long, locating a buffer near the PCM1850/1851
and minimizing load capacitance is recommended in order to minimize the digital-analog crosstalk and maximize the
dynamic performance of the ADC.
System Clock
Because the PCM1850/1851 operates based on a system clock, the quality of the system clock can influence dynamic
performance. Therefore, it is recommended to consider the system clock duty, jitter, and the time difference between the
system clock transition and the BCK or LRCK transition in slave mode.
相關(guān)PDF資料
PDF描述
PCM1850PJT 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
PCM1850PJTR 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
PCM1850 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
PCM1851 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
PCM1851PJT 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
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