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| 型號(hào)： | PCM1851APJTR |
| 英文描述： | 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 ⅴ 2-CHANNEL MUX AND PGAE |
| 中文描述： | 24位，96千赫立體聲A / D轉(zhuǎn)換器6ⅴ2通道MUX和PGAE |
| 文件頁(yè)數(shù)： | 14/32頁(yè) |
| 文件大?。?/td> | 409K |
| 代理商： | PCM1851APJTR |
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DETAILED DESCRIPTION
SYSTEM CLOCK
The PCM1850A/1851A supports 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
as the system clock, where f
S
is the audio
sampling frequency. The system clock must be supplied on SCKI (pin 7).
t
(SCKH)
SCKI
t
(SCKL)
2 V
0.8 V
H
L
T0005-11
PCM1850A
PCM1851A
SLES173–MARCH 2006
The PCM1850A/1851A has a system clock detection circuit which automatically senses if the system clock is
operating at 256 f
S
, 384 f
S
, 512 f
S
, or 768 f
S
in slave mode. In master mode, the system clock frequency must be
selected by mode control via the serial port. The 768-f
S
system clock is not available in master mode or for f
S
=
88.2 kHz and 96 kHz in the slave mode. The system clock is divided into 128 f
and 64 f
automatically, and
these frequencies are used to operate the digital filter and the delta-sigma modulator, respectively.
Table 1
shows the relationship of typical sampling frequency to system clock frequency, and
Figure 20
shows
system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SYSTEM CLOCK FREQUENCY (MHz)
384 f
S
12.288
16.9344
18.432
24.576
33.8688
36.864
SAMPLING RATE FREQUENCY
(kHz)
256 f
S
8.192
11.2896
12.288
16.384
22.5792
24.576
512 f
S
16.384
22.5792
24.576
32.768
45.1584
49.152
768 f
S(1)
24.576
33.8688
36.864
49.152
—
—
32
44.1
48
64
88.2
96
(1)
Slave mode only
SYMBOL
t
(SCKH)
t
(SCKL)
PARAMETER
MIN
8
8
MAX
UNIT
ns
ns
System clock pulse duration, HIGH
System clock pulse duration, LOW
Figure 20. System Clock Timing
14
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