參數(shù)資料
型號: PCM1850PJTR
英文描述: 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
中文描述: 24位,96千赫立體聲A / D轉(zhuǎn)換器6 × 2通道的MUX和PGA
文件頁數(shù): 23/30頁
文件大?。?/td> 370K
代理商: PCM1850PJTR
PCM1850
PCM1851
SLES108
MARCH 2004
www.ti.com
23
CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850)
Figure 29 shows a detailed timing diagram for the serial control interface of the PCM1850. These timing parameters are
critical for proper control port operation.
t
(MCH)
1.4 V
MS
t
(MSS)
LSB
1.4 V
1.4 V
t
(MCL)
t
(MHH)
t
(MSH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
SYMBOL
PARAMETERS
MIN
MAX
UNITS
t
(MCY)
t
(MCL)
t
(MCH)
t
(MHH)
t
(MSS)
t
(MSH)
t
(MDH)
t
(MDS)
MC pulse cycle time
100
ns
MC LOW level time
40
ns
MC HIGH level time
40
ns
MS HIGH level time
80
ns
MS falling edge to MC rising edge
MS hold time
(1)
15
ns
15
ns
MD hold time
15
ns
MD setup time
15
ns
(1)
MC rising edge for LSB to MS rising edge.
Figure 29. PCM1850 Control Interface Timing
I
2
C SERIAL CONTROL PORT FOR MODE CONTROL (PCM1851)
The user-programmable built-in function of the PCM1851 can be controlled through the I
2
C-format serial control port, SDA
(pin 32) and SCL (pin 31). The PCM1851 supports the I
2
C serial bus and the data transmission protocol for standard mode
as a slave device. This protocol is explained in the I
2
C specification 2.0.
Slave Address
MSB
LSB
1
0
0
1
0
1
ADR
R/nW
The PCM1851 has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to
100101. The last bit of the address byte is the device select bit, which can be user-defined by the ADR pin (pin 30). A
maximum of two PCM1851s can be connected on the same bus at one time. Each PCM1851 responds when it receives
its own slave address.
相關(guān)PDF資料
PDF描述
PCM1850 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
PCM1851 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
PCM1851PJT 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA
PCM2702 16-Bit Stereo DIGITAL-TO-ANALOG CONVERTER with Interface
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