參數(shù)資料
型號: PCM1808PWRG4
英文描述: SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER
中文描述: 單端模擬輸入24位,96千赫立體聲A / D轉(zhuǎn)換器
文件頁數(shù): 11/23頁
文件大?。?/td> 214K
代理商: PCM1808PWRG4
www.ti.com
SYSTEM CLOCK
The PCM1808 supports 256 f
, 384 f
and 512 f
as system clock, where f
S
is the audio sampling frequency.
The system clock must be supplied on SCKI (pin 6).
SCKI
0.8 V
SCKI
2 V
t
w(SCKL)
t
w(SCKH)
T0005B07
FADE-IN AND FADE-OUT FUNCTIONS
The PCM1808 has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions come
into operation in some cases as described in several following sections. The level changes from 0 dB to mute or
mute to 0 dB are performed using calculated pseudo S-shaped characteristics with zero-cross detection.
Because of the zero-cross detection, the time needed for the fade in and fade out depends on the analog input
frequency (f
in
). It takes 48/f
in
until processing is completed. If there is no zero cross during 8192/f
S
, DOUT is
faded in or out by force during 48/f
S
(TIME OUT).
Figure 18
illustrates the fade-in and fade-out operation
processing.
PCM1808
SLES177A–APRIL 2006–REVISED AUGUST 2006
The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating
at 256 f
, 384 f
, or 512 f
in slave mode. In master mode, the system clock frequency must be controlled
through the serial control port, which uses MD1 (pin 111) and MD0 (pin 10). The system clock is divided down
automatically to generate frequencies of 128 f
S
and 64 f
S
, which are used to operate the digital filter and the
delta-sigma modulator, respectively.
Table 1
shows some typical relationships between sampling frequency and system clock frequency, and
Figure 17
shows system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
384 f
S
3.072
6.144
12.288
16.9344
18.432
24.576
33.8688
36.864
256 f
S
2.048
4.096
8.192
11.2896
12.288
16.384
22.5792
24.576
512 f
S
4.096
8.192
16.384
22.5792
24.576
32.768
45.1584
49.152
8
16
32
44.1
48
64
88.2
96
SYMBOL
t
w(SCKH)
t
w(SCKL)
PARAMETER
MIN
8
8
40%
MAX
UNIT
ns
ns
System clock pulse duration, HIGH
System clock pulse duration, LOW
System clock duty cycle
60%
Figure 17. System Clock Timing
11
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