參數(shù)資料
型號(hào): PCM1808PWR
英文描述: SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER
中文描述: 單端模擬輸入24位,96千赫立體聲A / D轉(zhuǎn)換器
文件頁數(shù): 17/23頁
文件大?。?/td> 214K
代理商: PCM1808PWR
www.ti.com
BCK
LRCK
DOUT
t
(BCKH)
t
(BCKL)
t
(CKLR)
t
(LRCP)
t
(BCKP)
t
(CKDO)
t
(LRDO)
0.5 V
DD
0.5 V
DD
0.5 V
DD
T0018-02
BCK
SCKI
t
(SCKBCK)
1.4 V
0.5 V
DD
T0074-01
t
(SCKBCK)
PCM1808
SLES177A–APRIL 2006–REVISED AUGUST 2006
SYMBOL
t
(BCKP)
t
(BCKH)
t
(BCKL)
t
(CKLR)
t
(LRCP)
t
(CKDO)
t
(LRDO)
t
r
t
f
PARAMETER
MIN
150
65
65
–10
10
–10
–10
TYP
1/(64 f
S
)
MAX
2000
1200
1200
20
125
20
20
20
20
UNIT
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
BCK period
BCK pulse duration, HIGH
BCK pulse duration, LOW
Delay time, BCK falling edge to LRCK valid
LRCK period
Delay time, BCK falling edge to DOUT valid
Delay time, LRCK edge to DOUT valid
Rise time of all signals
Fall time of all signals
1/f
S
NOTE: Timing measurement reference level is 0.5 V
DD
. Rise and fall times are from 10% to 90% of the input/output signal
swing. Load capacitance of all signals is 20 pF.
Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)
SYMBOL
t
(SCKBCK)
PARAMETER
MIN
5
TYP
MAX
30
UNIT
ns
Delay time, SCKI rising edge to BCK edge
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 V
DD
for output. Load capacitance of BCK is 20 pF.
This timing is applied when SCKI frequency is less than 25 MHz.
Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output)
17
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