參數(shù)資料
型號: PCM1804
英文描述: FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER
中文描述: 全差分模擬輸入24位,192千赫立體聲A / D轉換器
文件頁數(shù): 23/31頁
文件大?。?/td> 470K
代理商: PCM1804
PCM1804
SLES022A
DECEMBER 2001
23
www.ti.com
PRINCIPLES OF OPERATION
interface timing for PCM (continued)
t(LRCP)
tw(BCKH)
tw(BCKL)
t(LRHD)
t(LRSU)
t(BCKP)
t(CKDO)
t(LRDO)
1.4 V
1.4 V
0.5 VDD
LRCK
BCK
DATA
PARAMETERS
MIN
TYP
MAX
UNIT
BCK period, t(BCKP)
BCK pulse width high, tw(BCKH)
BCK pulse width low, tw(BCKL)
LRCK setup time to BCK rising edge, t(LRSU)
LRCK hold time to BCK rising edge, t(LRHD)
LRCK period, t(LRCP)
Delay time BCK falling edge to DATA valid, t(CKDO)
Delay time LRCK edge to DATA valid, t(LRDO)
Rising time of all signals, tr
Falling time of all signals, tf
1/(64 fS)
1/(64 fS)
1/(48 fS)
32
ns
32
ns
12
ns
12
ns
1/fS
5
25
ns
5
25
ns
10
ns
10
ns
NOTES: A. Rising and falling time is measured from 10% to 90% of IN/OUT signals swing.
B. Load capacitance of DATA/DSDR signal is 10 pF.
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
interface timing for DSD
Figure 39 and Figure 40 illustrate the interface timing for DSD.
Dn
3
Dn
2
Dn
1
Dn
Dn+1
Dn+2
Dn+3
Dn
3
Dn
2
Dn
1
Dn
Dn+1
Dn+2
Dn+3
DSDBCK
DSDL
DSDR
Figure 39. Audio Data Format
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