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參數(shù)資料
| 型號： | PCM1801 |
| 英文描述： | 16-Bit, Stereo, Audio ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位，立體聲，音頻模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 101K |
| 代理商： | PCM1801 |
10
PCM1801
THEORY OF OPERATION
PCM1801 consists of a bandgap reference, two channels of
a single-to-differential converter, a fully differential 5th-
order delta-sigma modulator, a decimation filter (including
digital high pass), and a serial interface circuit. The Block
Diagram illustrates the total architecture of PCM1801, the
Analog Front-End diagram illustrates the architecture of the
single-to-differential converter, and the anti-aliasing filter is
illustrated in the Block Diagram. Figure 1 illustrates the
architecture of the 5th-order delta-sigma modulator and
transfer functions.
An internal high precision reference with two external capaci-
tors provides all reference voltages which are required by the
converter, and defines the full-scale voltage range of both
channels. The internal single-ended to differential voltage
converter saves the design, space and extra parts needed for
external circuitry required by many delta-sigma converters.
The internal full differential architecture provides a wide
dynamic range and excellent power supply rejection perfor-
mance.
The input signal is sampled at 64x oversampling rate,
eliminating the need for a sample-and-hold circuit, and
simplifying anti-alias filtering requirements. The 5th-order
delta-sigma noise shaper consists of five integrators which
use a switched-capacitor topology, a comparator and a
feedback loop consisting of a 1-bit DAC. The delta-sigma
modulator shapes the quantization noise, shifting it out of
the audio band in the frequency domain. The high order of
the modulator enables it to randomize the modulator out-
puts, reducing idle tone levels.
The 64f
S
, 1-bit stream from the modulator is converted to
1f
S
, 16-bit digital data by the decimation filter, which also
acts as a low-pass filter to remove the shaped quantization
noise. The DC components are removed by a digital high-
pass filter, and the filtered output is converted to time-
multiplexed serial signals through a serial interface which
provides flexible serial formats.
SYSTEM CLOCK
The system clock for PCM1801 must be either 256f
S
, 384f
S
,
or 512f
S
, where f
S
is the audio sampling frequency. The
system clock must be supplied on SCKI (pin 5).
PCM1801 also has a system clock detection circuit which
automatically senses if the system clock is operating at
256f
S
, 384f
S
, or 512f
S
.
When 384f
S
and 512f
S
system clock are used, the PCM1801
automatically divides these clocks down to 256f
S
internally.
This 256f
S
clock is used to operate the digital filter and the
modulator. Table I lists the relationship of typical sampling
frequencies and system clock frequencies. Figure 2 illus-
trates the system clock timing.
FIGURE 1. Simplified Diagram of the PCM1801 5th-Order Delta-Sigma Modulator.
FIGURE 2. System Clock Timing.
SYSTEM CLOCK FREQUENCY
(MHz)
256f
S
8.1920
11.2896
12.2880
384f
S
12.2880
16.9340
18.4320
512f
S
16.3840
22.5792
24.5760
32
44.1
48
TABLE I. System Clock Frequencies.
SAMPLING RATE FREQUENCY
(kHz)
+
+
–
+
+
+
5th SW-CAP
Integrator
4th SW-CAP
Integrator
3rd SW-CAP
Integrator
2nd SW-CAP
Integrator
1st SW-CAP
Integrator
+
+
+
+
–
+
+
–
1-Bit
DAC
H(z)
Qn(z)
Analog In
X(z)
Digital Out
Y(z)
Y(z) = STF(z) X(z) + NTF(z) Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]
Comparator
t
CLKIH
System Clock Pulse Width High
t
CLKIH
t
CLKIL
12ns (min)
System Clock Pulse Width Low
12ns (min)
t
CLKIL
SCKI
2.0V
0.8V
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