參數(shù)資料
型號(hào): PCM1800
英文描述: Single-Ended Analog Input 20-Bit Stereo ANALOG-TO-DIGITAL CONVERTER
中文描述: 單端模擬輸入20位立體聲模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 15/15頁(yè)
文件大?。?/td> 172K
代理商: PCM1800
15
PCM1800
FIGURE 11. Typical Circuit Connection.
V
IN
PINS
A 1.0
μ
F tantalum capacitor is recommended as an AC-
coupling capacitor which establishes a 5.3Hz cut-off fre-
quency. If a higher full-scale input voltage is required, the
input voltage range can be increased by adding a series
resistor to the V
IN
pins.
V
REF
INPUTS
A 4.7
μ
F tantalum capacitor is recommended between V
REF
1,
V
REF
2, and REFCOM to ensure low source impedance for
the ADC’s references. These capacitors should be located as
close as possible to the V
REF
1 or V
REF
2 pin to reduce
dynamic errors on the ADC’s references. The REFCOM pin
should also be connected directly to AGND under the parts.
C
IN
P and C
IN
N INPUTS
A 470pF to 1000pF film capacitor is recommended between
C
IN
PL and C
IN
NL, C
IN
PR and C
IN
NR to create an anti-
aliasing filter, which will have an 170kHz to 80kHz cut-off
frequency. These capacitors should be located as close as
possible to the C
IN
P and C
IN
N pins to avoid introducing
unexpected noise or dynamic errors into the delta-sigma
modulator.
DOUT, BCK, LRCK, FSYNC PINS
The DOUT, BCK, LRCK and FSYNC pins in Master Mode
have a large load drive capability, but locating the buffer
near the PCM1800 and minimizing the load capacitance is
recommended in order to minimize the digital analog crosstalk
and to maximize dynamic performance potential.
SYSTEM CLOCK
The quality of the system clock can influence dynamic
performance in the PCM1800. The duty cycle, jitter, and
threshold voltage at the system clock input pin must be
carefully managed. When power is supplied to the part, the
system clock, bit clock (BCK), and a word clock (LRCK)
should also be supplied simultaneously. Failure to supply
the audio clocks will result in a power dissipation increase
of up to three times normal dissipation and may degrade
long-term reliability if the maximum power dissipation limit
is exceeded.
RSTB Control
If the capacitance between V
REF
1 and V
REF
2 exceeds 4.7
μ
F,
an external reset control delay time circuit must be used.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SYSCLK
DOUT
BCK
LRCK
/RESET
BYPASS
FORMAT0
FORMAT1
MODE0
MODE1
SYNC
+
4.7μF
+
1.0μF
(2)
Analog
Front-End
Analog
Front-End
Delta-Sigma
Decimation Filter
Digital Audio Interface
Reset
Clock
Audio
Data
Processor
Pin Program
or Control
Line In Left-Channel
+
1.0μF
(2)
Line In Right-Channel
GND
+5V
+
4.7μF
NOTES: (1) Bypass capacitor = 0.1μF ceramic and 10μF tantalum, depending on layout
and power supply. (2) A 1.0μF capacitor gives 5.3Hz (
τ
= 1μF x 30k
) cut-off frequency
of input HPF in normal operation and requires power-on settling time with 60ms time
constant in power on initialization period.
Ref
0.1μF/10μF
(1)
0.1μF/10μF
(1)
+
+
C
470pF
C
470pF
相關(guān)PDF資料
PDF描述
PCM1800E Single-Ended Analog Input 20-Bit Stereo ANALOG-TO-DIGITAL CONVERTER
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