參數(shù)資料
型號: PCM1753DBQ
英文描述: 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192千赫采樣增強的多級Δ-Σ,音頻數(shù)字模擬轉換器
文件頁數(shù): 13/33頁
文件大?。?/td> 309K
代理商: PCM1753DBQ
PCM1753
PCM1754
PCM1755
SLES092A – OCTOBER 2003 – REVISED AUGUST 2004
www.ti.com
13
Power-On Reset Functions
The PCM1753/54/55 includes a power-on reset function. Figure 20 shows the operation of this function. With
the system clock active and V
CC
> 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The
initialization sequence requires 1024 system clocks from the time V
CC
> 3 V (typical, 2.2 V to 3.7 V). After the
initialization period, the PCM1753/55 is set to its reset default state, as described in the
Mode Control Registers
section of this data sheet.
During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or V
CC
/2.
After the reset period, an internal register is initialized in the next 1/f
S
period and if SCK, BCK, and LRCK are
provided continuously, the PCM1753/54/55 provides proper analog output with unit group delay against the
input data.
Reset
Reset Removal
1024 System Clocks
V
CC
3.7 V (Max)
3.0 V (Typ)
2.2 V (Min)
Internal Reset
System Clock
Don’t Care
Figure 20.
Power-On Reset Timing
相關PDF資料
PDF描述
PCM1754 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
PCM1755 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
PCM1755DBQ 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
PCM1754DBQ 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
PCM1754DBQR 24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
相關代理商/技術參數(shù)
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