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參數(shù)資料
| 型號(hào)： | PCM1741 |
| 英文描述： | %2B3.3V Single-Supply, 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 3.3V的單電源，24位，96kHz采樣加強(qiáng)多層次，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 325K |
| 代理商： | PCM1741 |
PCM1741
SBAS175
8
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1741 requires a system clock for operating the
digital interpolation filters and multilevel delta-sigma modu-
lators. The system clock is applied at the SCK input (pin 16).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multi-
clock generator from Texas Instruments is an excellent choice
for providing the PCM1741 system clock.
POWER-ON RESET FUNCTIONS
The PCM1741 includes a power-on reset function, as shown in
Figure 2. With the system clock active, and V
DD
> 2.0V (typical
1.6V to 2.4V), the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time V
DD
> 2.0V. After the initialization period, the PCM1741
will be set to its reset default state, as described in the Mode
Control Register section of this data sheet.
During the reset period (1024 system clocks), the analog
outputs are forced to the bipolar zero level, or V
CC
/2. After
the reset period, the internal register is initialized in the next
1/f
S
period and, if SCK, BCK, and LRCK are provided
continuously, the PCM1741 provides proper analog output
with unit group delay against the input data.
FIGURE 1. System Clock Input Timing.
SAMPLING
FREQUENCY
256f
S
384f
S
512f
S
768f
S
8kHz
16kHz
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
2.0480
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
3.0720
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
4.0960
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
6.1440
12.2880
24.5760
33.8688
36.8640
See Note (1)
See Note (1)
NOTE: (1) The 768f
S
system clock rate is not supported for f
S
> 64kHz.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
FIGURE 2. Power-On Reset Timing.
1024 System Clocks
Reset
Reset Removal
V
DD
Internal Reset
2.4V
2.0V
1.6V
0V
System Clock
Don't Care
t
SCKH
t
SCKL
2.0V
0.8V
System Clock
System clock pulse
cycle time
(1)
“
H
”
“
L
”
System Clock Pulse Width HIGH t
SCKH
: 7ns (min)
System Clock Pulse Width LOW t
SCKL
: 7ns (min)
NOTE: (1) 1/256f
S
, 1/384f
S
, 1/512f
S
, and 1/768f
S
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1741/E2K | 制造商:BB 制造商全稱:BB 功能描述:+3.3V Single-Supply, 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER |
| PCM1741E | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC +3.3V 24-Bit 96kHz Samp Enh Mult RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1741E/2K | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC +3.3V 24-Bit 96kHz Samp Enh Mult RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1741E/2KG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC +3.3V 24-Bit 96kHz Samp Enh Mult RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1741EG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC +3.3V 24-Bit 96kHz Samp Enh Mult RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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