參數(shù)資料
型號(hào): PCM1740E
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER with VCXO and PLL
中文描述: 立體聲音頻數(shù)模轉(zhuǎn)換器與石英振蕩器和PLL
文件頁數(shù): 14/20頁
文件大?。?/td> 359K
代理商: PCM1740E
14
PCM1740
SYS
Audio System Clock (or SCKO)
The SYS bit is used to select the system clock (or SCKO) frequency, either 256f
S
or 384f
S
.
SYS = 0
SYS = 1
384f
S
(default)
256f
S
DSR0
DSR1
Sampling Frequency Multiplier
The DSR0 and DSR1 bits are used to select the multiplier used in conjunction with the SF0 and SF1 bits.
DSR1
0
0
1
1
DSR0
0
1
0
1
Multiplier
Normal, x1 (default)
Double, x2
Half, x 1/2
Reserved
SF0
SF1
Sampling Frequency Select
The SF0 and SF1 bits are used to select the sampling frequency group (32kHz, 44.1kHz, or 48kHz). The DSR0
and DSR1 bits, described previously, are used to select the multiplier.
SF1
0
0
1
1
SF0
0
1
0
1
Sampling Frequency Group
44.1kHz Group ( 22.05kHz, 44.1kHz, or 88.2kHz) (default)
48 kHz Group (24kHz, 48kHz, or 96kHz)
32 kHz Group (16kHz, 32kHz, or 64kHz)
Reserved
LD
Attenuation Data Load Control
The LD bit is used to simultaneously set the Left and Right digital attenuation data. When LD is set to “1”, the
digital attenuation data given by Registers 0 and 1 is loaded for the Left and Right channels. When LD is set
to “0”, updates to Registers 0 and 1 are ignored, and the attenuation settings remain as previously programmed
until LD is set to “1”.
LD = 0
LD = 1
Disabled
Enabled: Left and Right Attenuation Data Updated Simultaneously
IZD
Infinite Zero Detect Mute
The IZD bit is used to enable/disable the infinite zero detect mute function. The PCM1740 includes infinite zero
detection logic that monitors the audio data at the DATA input (pin 18). If the audio data for both the Left and
Right channels is all zeros for 65,536 continuous BCK clock cycles, the zero flag will be activated and output
amplifier will be disconnected from the output of the delta-sigma modulator. The output amplifier’s input is
switched to the DC common mode voltage. This forces V
OUT
L and V
OUT
R to V
CC
/2. The ZERO output flag (pin
16) is not affected by the setting of this bit.
IZD = 0
IZD = 1
Disabled (default)
Enabled
OPE
DAC Operation Control
The OPE bit is used to enable/disable the operation of the D/A converters. When enabled, the DAC outputs are
connected to the output amplifier for normal operation. When disabled, the output amplifier is disconnected from
the DAC output and switched to the DC common mode voltage. This forces V
OUT
L and V
OUT
R to V
CC
/2.
OPE = 0
OPE = 1
Enabled: Normal Operation(default)
Disabled: Outputs forced to V
CC
/2
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 4
res
res
res
res
res
1
0
0
res
res
res
res
res
OPE
IZD
LD
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCM1740E/2K 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1740E/2KG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1740E-1/2K 制造商:Texas Instruments 功能描述:
PCM1740EG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo DAC w/Prog PLL&VCXO RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
PCM1741 制造商:BB 制造商全稱:BB 功能描述:+3.3V Single-Supply, 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER